1 Quantum Enabling Technology Materials Research for Superconducting Quantum Computing Materials P.I. - D. P. Pappas Affiliates: Jeff Kline Fabio da Silva Students:Will Kindel Teresa Osminer Postdocs*David Wisbee

2 Anatomy of a superconducting qubit Substrate Insulator (if subs. conductive) Bottom electrode Junction - Tunnel barrier Insulator Wiring Top electrode

Materials development – can we reduce decoherence? Absorption in dielectric & junction (a-SiO 2 ) & (a-AlO 2 ) Si a-SiO x Al Focus on: Insulators: along traces & around junction in substrate crossovers Tunnel barrier: Between top and bottom electrode Electrode surfaces: Flux noise from surface spins AlOx

=> With & without SiO2 over the capacitor C/2 L Dissipation is in SiO2 dielectric of the capacitor! ~P out Resonant circuits have low Q at low T, P

Qubit spectroscopy splittings due to two-level systems in Junction tunnel barrier Increase the bias voltage (tilt) Frequency of |0> => |1> transition goes down Resonances Increase bias

DC SQUIDs: S  1/2 (1Hz) vs. T At low T: S  1/2 (1Hz) ≈ 7 ± 3  0 Hz -1/2 Loop materials: Nb (A1-4, F1) Pb (C2) PbIn (A5, B1, C1, E1,2) Loop effective areas: 1,400  m 2 – 200,000  m 2 ( Wellstood, Urbina and Clarke (1987)

Superconducting JJ qubits – mtls. & meas. Primary NIST differentiator – Crystalline junction material Secondary differentiator – Crystalline bottom electrodes UHV & processing combination Enabling development: Substrate preparation Development of low loss insulators priority – a-Si:H, a-C:H, Si(111) Benchmarks – a-SiOx, a-SiN Facilities ADR with I/V and RF capablility RF capability on PPMS

Original Statement of Work Tasks: 1)Substrate preparation 2)Bottom electrode 3)Epitaxial barrier development 4)Top Electrode 5)Dielectric layers 6)Top & bottom wiring layers

Progress Studied substrates from different vendors ( collaboration w/LL, DARPA) - Task 1 – Obtained 3” wafers of Sapphire (0001) – Measured roughness using AFM Developed Qubit test platform for junction tests - Task 1-6 – 12 qubit test die – quickly find optimized junctions – Devices fabricated here – Measurements done– 500 ns T1!! Developed insulator test platform – Task 1-6 – Make simple structure to test loss in various dielectrics – new set of dies – Devices fabricated here – Measurements show absorption – sent to JPL Fabricated SQUIDs and measure noise – Task 1-6 – Various widths & flux trapping conditions – Fabricated Ru capped washers – Added Fe – Measured - Same noise level with Ru as Al & Re, reduced by factor of ML Fe Measure junctions in-house for quality control – Task 1-6 – ADR test facility built up – – Tested first junctions here last week Commissioned 3” chamber for epi Si(111)/Al(111)/Al2O3/Al(111) - Task 1-4

Task 1 - Wafer substrate AFM analysis CG wafer surfaceES wafer surfaceSG wafer surface Acquired wafers from 3 manufacturers Epi-stone (ES) & Saint Gobain (SG), and Crystal GmbH (CG) Conducted AFM on them in collaboration with LL under DARPA CG & ES wafers looked best – show atomic steps SG wafer surface looked poor, lots of scratches, no steps. Note – Growth of Re on SG wafers actually show the best RHEED!

Progress Studied substrates from different vendors ( collaboration w/LL, DARPA) - Task 1 – Obtained 3” wafers of Sapphire (0001) – Measured roughness using AFM Developed Qubit test platform for junction tests - Task 1-6 – 12 qubit test die – quickly find optimized junctions – Devices fabricated here – Measurements done– 500 ns T1!! Developed insulator test platform – Task 1-6 – Make simple structure to test loss in various dielectrics – new set of dies – Devices fabricated here – Measurements show absorption – sent to JPL Fabricated SQUIDs and measure noise – Task 1-6 – Various widths & flux trapping conditions – Fabricated Ru capped washers – Added Fe – Measured - Same noise level with Ru as Al & Re, reduced by factor of ML Fe Measure junctions in-house for quality control – Task 1-6 – ADR test facility built up – – Tested first junctions here last week Commissioned 3” chamber for epi Si(111)/Al(111)/Al2O3/Al(111) - Task 1-4

Task Qubit Die Layout Bias coil Qubit loop DC-SQUID Allows us to test a wide range of junction sizes even with low yield!

Progress Studied substrates from different vendors ( collaboration w/LL, DARPA) - Task 1 – Obtained 3” wafers of Sapphire (0001) – Measured roughness using AFM Developed Qubit test platform for junction tests - Task 1-6 – 12 qubit test die – quickly find optimized junctions – Devices fabricated here – Measurements done– 500 ns T1!! Developed insulator test platform – Task 1-6 – Make simple structure to test loss in various dielectrics – new set of dies – Devices fabricated here – Measurements show absorption – sent to JPL Fabricated SQUIDs and measure noise – Task 1-6 – Various widths & flux trapping conditions – Fabricated Ru capped washers – Added Fe – Measured - Same noise level with Ru as Al & Re, reduced by factor of ML Fe Measure junctions in-house for quality control – Task 1-6 – ADR test facility built up – – Tested first junctions here last week Commissioned 3” chamber for epi Si(111)/Al(111)/Al2O3/Al(111) - Task 1-4

Task 5 - Quantum Materials: Low loss insulators Test platform do develop low loss insulators – Collaborating with Ben Mazin to design antenna test platform – Measurements made on a-SiOx as a reference Q ~ 1000 – Just started making measurments on a-ALD-AlOx, – While measurements in progress, preparing SiN, a-C, a-Ge

Progress Studied substrates from different vendors ( collaboration w/LL, DARPA) - Task 1 – Obtained 3” wafers of Sapphire (0001) – Measured roughness using AFM Developed Qubit test platform for junction tests - Task 1-6 – 12 qubit test die – quickly find optimized junctions – Devices fabricated here – Measurements done– 500 ns T1!! Developed insulator test platform – Task 1-6 – Make simple structure to test loss in various dielectrics – new set of dies – Devices fabricated here – Measurements show absorption – sent to JPL Fabricated SQUIDs and measure noise – Task 1-6 – Various widths & flux trapping conditions – Fabricated Ru capped washers – Added Fe – Measured - Same noise level with Ru as Al & Re, reduced by factor of ML Fe Measure junctions in-house for quality control – Task 1-6 – ADR test facility built up – – Tested first junctions here last week Commissioned 3” chamber for epi Si(111)/Al(111)/Al2O3/Al(111) - Task 1-4

Task 6 - Flux noise vs. F on Ru capped Al with 0.2 ML Fe on top Red curve – SQUID washer w/ Ru cap Blue Curve – Same SQUID washer w/ Ru cap ML Fe on top Factor of 2 reduction in noise due to Fe!! (rather than increasing noise)

Progress Studied substrates from different vendors ( collaboration w/LL, DARPA) - Task 1 – Obtained 3” wafers of Sapphire (0001) – Measured roughness using AFM Developed Qubit test platform for junction tests - Task 1-6 – 12 qubit test die – quickly find optimized junctions – Devices fabricated here – Measurements done– 500 ns T1!! Developed insulator test platform – Task 1-6 – Make simple structure to test loss in various dielectrics – new set of dies – Devices fabricated here – Measurements show absorption – sent to JPL Fabricated SQUIDs and measure noise – Task 1-6 – Various widths & flux trapping conditions – Fabricated Ru capped washers – Added Fe – Measured - Same noise level with Ru as Al & Re, reduced by factor of ML Fe Measure junctions in-house for quality control – Task 1-6 – ADR test facility built up – – Tested first junctions here last week Commissioned 3” chamber for epi Si(111)/Al(111)/Al2O3/Al(111) - Task 1-4

I-V curve from epitaxial barrier

Results of our junctions: R (1/G) vs. T for Al/AlO x /Al tunnel jctn. Signatures of quantum tunneling – R increases as T decreases – Zero slope at low T Zero-bias resistance In collaboration with Oh et al (Rutgers)

Progress Studied substrates from different vendors ( collaboration w/LL, DARPA) - Task 1 – Obtained 3” wafers of Sapphire (0001) – Measured roughness using AFM Developed Qubit test platform for junction tests - Task 1-6 – 12 qubit test die – quickly find optimized junctions – Devices fabricated here – Measurements done– 500 ns T1!! Developed insulator test platform – Task 1-6 – Make simple structure to test loss in various dielectrics – new set of dies – Devices fabricated here – Measurements show absorption – sent to JPL Fabricated SQUIDs and measure noise – Task 1-6 – Various widths & flux trapping conditions – Fabricated Ru capped washers – Added Fe – Measured - Same noise level with Ru as Al & Re, reduced by factor of ML Fe Measure junctions in-house for quality control – Task 1-6 – ADR test facility built up – – Tested first junctions here last week Commissioned 3” chamber for epi Si(111)/Al(111)/Al2O3/Al(111) - Task 1-4

Lesker 3” deposition chamber

Note: Test devices include all/most layers => Hard to separate original tasks! Re-parse SOW Tasks to reflect project goals. 1)Substrate preparation 2)Bottom electrode 3)Epitaxial barrier dev. 4)Top Electrode 5)Dielectric layers 6)Top & bottom wiring 1)Understand tunneling process 2)Devices on alternative substrates 3)Develop high Q circuits 4)Study noise in devices 5)Test coherence advances Still the same scope of work. Allows us to make Gantt chart directly from SOW.

Detailed subtasks 1.Understand tunnel process in epi-barriers 1.Tool up to measure I-V curves in-house with ADR 2.Measurement of samples at low temperature 3.Reduce spectroscopy splitting further using different tunnel barriers 4.Study materials doping in barriers 5.Study device/junction failure 2.Develop alternative substrates 1.Research & indentify new systems 2.Tool up 3” chamber in clean room for identified system 3.Prepare substrates 4.Prepare bottom electrode 5.Prepare barriers 6.Prepare top electrode 7.Fabricate into test junctions 3.Develop high Q materials for low T, P applications 1.Tool up for measurements at 1.7 K and 60 mK 2.Fabricate L-C circuits & test with SiO2 3.Tool up to grow a-Si dielectrics 4.Investigate new materials 5.Complete work with antenna resonators 4.Study noise due to surfaces & interfaces 1.Fabrication of SQUID devices 2. Identify source of decoherence loss 5.Test Coherence advances 1.Fabricate 12 qubit dies using optimal materials from above 2.Integrate & optimize all improvements into single qubit & measure

Gantt Chart