Digital Integrated Circuits A Design Perspective EE141 Digital Integrated Circuits A Design Perspective Timing Issues

Timing Definitions

Latch Parameters D Q Clk T Clk PWm tsu D thold tc-q td-q Q Delays can be different for rising and falling data transitions

Register Parameters D Q Clk T Clk thold D tsu tc-q Q Delays can be different for rising and falling data transitions

Clock Uncertainties Sources of clock uncertainty

Clock Non-idealities Clock skew Clock jitter Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clocking

Clock Skew and Jitter Clk tSK Clk tJS Both skew and jitter affect the effective cycle time Only skew affects the race margin

Positive and Negative Skew

Positive Skew Launching edge arrives before the receiving edge

Negative Skew Receiving edge arrives before the launching edge

Timing Constraints Minimum cycle time: T -  = tc-q + tsu + tlogic Worst case is when receiving edge arrives early (positive )

Impact of Jitter

Longest Logic Path in Edge-Triggered Systems TJI + d TSU Clk TClk-Q TLM T Latest point of launching Earliest arrival of next cycle

Shortest Path Clk TClk-Q TLm Clk TH Earliest point of launching Data must not arrive before this time Nominal clock edge

Clock Skew

Clock Distribution H-tree Clock is distributed in a tree-like fashion

More realistic H-tree [Restle98]

The Grid System No rc-matching Large power

Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 1) Completion is ensured by careful timing analysis 2) Ordering of events is implicit in logic Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol

Synchronous Pipelined Datapath

Self-Timed Pipelined Datapath

Completion Signal Generation

Completion Signal Using Current Sensing

Hand-Shaking Protocol Two Phase Handshake

2-Phase Handshake Protocol Advantage : FAST - minimal # of signaling events (important for global interconnect) Disadvantage : edge - sensitive, has state

4-Phase Handshake Protocol Also known as RTZ Slower, but unambiguous

4-Phase Handshake Protocol Implementation using Muller-C elements

Asynchronous-Synchronous Interface

Synchronizers and Arbiters Arbiter: Circuit to decide which of 2 events occurred first Synchronizer: Arbiter with clock f as one of the inputs Problem: Circuit HAS to make a decision in limited time - which decision is not important

A Simple Synchronizer • Data sampled on rising edge of the clock • Latch will eventually resolve the signal value, but ... this might take infinite time!

Arbiters

PLL-Based Synchronization

PLL Block Diagram

Phase Detector Output before filtering Transfer characteristic

Phase-Frequency Detector

PFD Response to Frequency

Charge Pump

Clock Generation using DLLs Delay-Locked Loop (Delay Line Based) fREF U Phase Det Charge Pump DL D Filter fO Phase-Locked Loop (VCO-Based) fREF U PD CP VCO D ÷N Filter fO

Delay Locked Loop

DLL-Based Clock Distribution

Digital Integrated Circuits A Design Perspective EE141 Digital Integrated Circuits A Design Perspective Arithmetic Circuits

A Generic Digital Processor

Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

Bit-Sliced Design

Bit-Sliced Datapath

Itanium Integer Datapath Fetzer, Orton, ISSCC’02

Adders

Full-Adder

The Binary Adder

The Ripple-Carry Adder Worst case delay linear with the number of bits td = O(N) tadder = (N-1)tcarry + tsum Goal: Make the fastest possible carry path circuit

Complimentary Static CMOS Full Adder 28 Transistors

Inversion Property

Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property

Transmission Gate Full Adder

Carry-Bypass Adder Also called Carry-Skip

Carry-Bypass Adder (cont.) tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

Carry Ripple versus Carry Bypass

Carry-Select Adder

Carry Select Adder: Critical Path

Linear Carry Select

Square Root Carry Select

Adder Delays - Comparison

LookAhead - Basic Idea

Carry Lookahead Trees Can continue building the tree hierarchically.

Tree Adders 16-bit radix-2 Kogge-Stone tree

Tree Adders 16-bit radix-4 Kogge-Stone Tree

Multipliers

The Binary Multiplication

The Array Multiplier

The MxN Array Multiplier — Critical Path

Carry-Save Multiplier

Wallace-Tree Multiplier

Wallace-Tree Multiplier

Multipliers —Summary

Shifters

The Binary Shifter

The Barrel Shifter Area Dominated by Wiring

4x4 barrel shifter Widthbarrel ~ 2 pm M