CHAPTER REPORT BY EUSTACE ASANGHANWA PHYSICAL TAMPER RESISTANCE Physical Tamper ResistanceEustace Asanghanwa 1

OVERVIEW OF TALK Ross Anderson on Physical Tamper Resistance Chapter report Critique Commentary on Tamper Resistance since 2000 Physical Tamper ResistanceEustace Asanghanwa2

KEY TAKE-AWAY A well-grounded understanding of the concept of tamper resistance Physical Tamper ResistanceEustace Asanghanwa3

ROSS ANDERSON ON PHYSICAL TAMPER RESISTANCE SECURITY ENGINEERING, 1 EDITION CHAPTER 14 Physical Tamper ResistanceEustace Asanghanwa4

HISTORICAL ATTACK TECHNIQUES Attack ObjectVulnerability Keys in PROMLaxity in custody Keys in sealed encasementsEncasement seals Tamper sensing barriersExposure from covering exposure EOL processors via dumpster divingMemory ‘permanent’ remanence RAM content via freezingLonger ‘temporal’ remanence Electromagnetic egressRemote analysis and key extraction Physical Tamper ResistanceEustace Asanghanwa5

SECURITY PROCESSOR EXAMPLES ChipSecurityNotes iButtonMediumKeys in RAM No tamper sensing barrier DS5002MediumBus encryption Cipher instruction search attack Capstone/ClipperMediumClaims tamper resistance 16-bit checksum easily brute forced Smartcards & MCUHighSecure application processor Security by obscurity until Pay-TV Physical Tamper ResistanceEustace Asanghanwa6

ATTACKER CLASSIFICATION ClassificationDescription Class 1Clever outsiders Class 2Knowledgeable insiders Class 3Funded organizations FIPS PUB (Effective 1994)Additive Requirements Level 1Basic security e.g. cryptography Level 2Tamper evidence Level 3Procedural tamper proofing Level 4Environmental tamper proofing Physical Tamper ResistanceEustace Asanghanwa7

ATTACKS ON SMARTCARDS Protocol Analysis Anti-tearing Cover V PP Single stepping Micro probing Memory linearization Cryptographic co-processor interfaces FIB through shields Physical Tamper ResistanceEustace Asanghanwa8

STATE OF ART SECURITY ARCHITECTURE State of Art Defense in depth (eliminate single points of failure) Tamper resistance versus tamper evidence Stop loss What goes wrong Architectural errors - Trusted card in an untrusted platform Security by obscurity targets IP protection Protocol failure from dangerous combination of commands Function creep as in multiuse cards Physical Tamper ResistanceEustace Asanghanwa9

BENEFITS OF TAMPER RESISTANT DEVICES Control information processing by linking to single physical token Assures data destruction at a definite and verifiable time Reduce the need to trust human operators Control value counters Physical Tamper ResistanceEustace Asanghanwa10

CRITIQUE Good Comprehensive on evolution of tamper resistance. Grasp on security principles. Opportunities for improvement Smartcard-centric. Some recommendations not consistent with provided principles e.g. Recommends “Using a proprietary (and complicated) encryption algorithm…” after recommending against home- brewed encryption schemes. Techniques behind times even for year Physical Tamper ResistanceEustace Asanghanwa11

CONCLUSION Security Engineering offers a good comprehensive history on tamper resistance with attention to security principles. Threat, tamper resistance, and evaluation techniques have evolved since publication of the first edition. I expect significant updates in the chapter on physical tamper resistance in the second edition (still awaiting my copy from Amazon). Physical Tamper ResistanceEustace Asanghanwa12

PERSONAL COMMENTARY ON PHYSICAL TAMPER RESISTANCE Physical Tamper ResistanceEustace Asanghanwa13

WHAT IS TAMPER RESISTANCE? Assuring achievement of security goals at all times Guiding Principles Assume capable adversaries Increase cost of analysis Reduce value of compromise Physical Tamper ResistanceEustace Asanghanwa14

SINCE 2000 [1 ST EDITION SECURITY ENGINEERING] Stronger adversaries Hackers are smarter Markets are wider fueling motivation Analysis equipment are more affordable Industry demands openness in techniques More professional analysis labs thanks to patent litigations Greater rigor on security evaluation Revision of FIPS PUB140-1 to FIPS PUB in 2002 Common Criteria (ISO/IEC 15408) major version revision from 2 to 3 currently at version 3.1. Physical Tamper ResistanceEustace Asanghanwa15

FIPS FIPS PUB (Effective 2002)Additive Requirements Level 1 Basic security e.g. cryptography Untrusted OS Level 2 Tamper evidence Trusted OS Role based authentication Common Criteria EAL 2+ Level 3 Procedural tamper proofing Identity based authentication Plaintext CSP on dedicated ports Common Criteria EAL 3+ Level 4 Environmental tamper proofing Zeroize CSPs on intrusion Common Criteria EAL 4+ Physical Tamper ResistanceEustace Asanghanwa16

COMMON MODERN DAY THREATS Micro-probing Security protocols Algorithm exploits Operational environment Operations timing Bug exploits Physical Tamper ResistanceEustace Asanghanwa17

CRITICAL ELEMENTS FOR SUCCESS IN IC TAMPER PROOFING Choice and implementation of algorithms Analog tamper monitors Quality of RNG Cost of analysis Practicality of exploits Courtesy Wikipedia Physical Tamper ResistanceEustace Asanghanwa18

RECAP Tamper resistance is about achieving security goals at all times Described technology-based methods are common but don’t have to be Other tamper proofing methods may include: Legislation (e.g. in banking networks) Cultural actions e.g. shaming Secured premises Eustace Asanghanwa19Physical Tamper Resistance

THANK YOU Physical Tamper ResistanceEustace Asanghanwa20