Lecture 131 Lecture 13: Other Devices on the XUP Board ECE 412: Microcomputer Laboratory

Lecture 132 Objectives A whirlwind tour of the parts on the XUP board that we haven’t used or talked about yet.

Lecture 133 Review Questions Why is the YUV format used by the video decoder more efficient than using an RGB format? The efficiency of YUV versus RGB lies in the fact that YUV is basically a compressed form of RGB. The encoding scheme takes advantage of the fact that the human eye is more sensitive to changes in brightness than changes in color. Therefore the YUV system gives more weight to the brightness (luminance) value of pixels. In RGB format, each pixel is required to have 3 bytes of information. In YUV format, only brightness data is sent for each individual pixel. The color data is only sent in 2 bytes for every-other pixel, and is shared between 2 neighboring pixels. Therefore, each set of 2 pixels features two brightness values (1 for each pixel) and 2 color values that are shared between the two, for a total of 4 bytes for 2 pixels. The same 2 pixels in RGB would take 6 bytes of space. This compression scheme allows YUV to be more efficient than RGB.

Lecture 134 Parts We’ll Cover AC97 CODEC and stereo amp LXT972A Ethernet Transceiver DS2401 serial interface SN ROM Also on XUP board: Serial ATA ports (Advanced Technology Attachment: hard disk standard created to replace the parallel ATA) MGT transceivers Serial port USB 2.0 (used for programming at present) SystemAce (used for Linux file system) We have documentation on these for anyone interested in using them in a project.

Lecture 135 XUP Development System Block Diagram

Lecture 136 LM4550 codec The LM4550 was designed specifically to provide a high quality audio path and provide all analog functionality in a PC audio system. It features full duplex stereo ADCs and DACs and analog mixers with access to 4 stereo and 4 mono analog inputs. Each mixer input has separate gain, attenuation and mute control and the mixers drive 1 mono and 2 stereo analog outputs, each with attenuation and mute control. The LM4550 provides a stereo headphone amplifier as one of its stereo outputs and also supports National’s 3D Sound stereo enhancement and a comprehensive sample rate conversion capability. The sample rate for the ADCs and DACs can be programmed separately with a resolution of 1 Hz to convert any rate in the range 4 kHz – 48 kHz. Sample timing from the ADCs and sample request timing for the DACs are completely deterministic to ease task scheduling and application software development.

Lecture 137 Review of Digital Sampling Sampling is the process of converting a signal (for example, a function of continuous time or space) into a numeric sequence (a function of discrete time or space). Basic Idea: If you take digital samples of an analog signal at a high enough rate, it is possible to convert the stream of digital samples back into an faithful copy of the original signal Nyquist-Shannon Sampling Theorem: The theorem states, in the original words of Shannon (where he uses "cps" for "cycles per second" instead of the modern unit hertz) –If a function f(t) contains no frequencies higher than W cps, it is completely determined by giving its ordinates at a series of points spaced 1/(2W) seconds apart.

Lecture 138 National LM4550 ADC/DAC Low-Pass Filter Stereo Analog Inputs Analog-to- Digital Converter Serial Data Low-Pass Filter Stereo Analog Outputs Digital-to- Analog Converter Serial Data

Lecture 139

10 More Specifics on LM4550VH ADC/DAC Both a stereo Analog-Digital Converter and a stereo Digital- Analog Converter. –One output directly connects to audio headphone amplifier –Digital data is based on the Audio Code ’97 (AC97) standard 18-bit accuracy (both input and output) –20-bit fields in AC97 (format require unused bits to be filled with zeros. –Serial digital PCM in/out Pulse-code modulation (PCM) is a digital representation of an analog signal Sample rate set by AC97 input and crystal frequency –Supports sample rates of 4-48kHz –XTAL_IN is MHz –22kHz is “conventional” high end of human hearing range.

Lecture 1311 AC97 Timing and Data Output frames –256 bits of data in a frame: 16-bit TAG slot, bit data slots –SDATA_IN: Serial data, an output of LM4550 A new Output Frame is signaled with a low-to-high transition of SYNC. The LM4550 checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-high transition on SYNC) before 256 bits are received from the old Frame then the new Frame is ignored.

Lecture 1312 SYNC is sampled with the rising edge of BIT_CLK. The first tag bit in the Frame (“Valid Frame”) should be clocked from the controller by the next rising edge of BIT_CLK and sampled by the LM4550 on the following falling edge. AC97 Timing and Data (cont’)

Lecture 1313 Intel LXT972A Ethernet Transceiver 10/100 Mbit Dual-Speed Transceiver –A single-port Fast Ethernet 10/100 Transceiver that supports 10 Mbps and 100 Mbps networks. –It complies with all applicable requirements of IEEE –It can directly drive either a 100BASE-TX line (up to 140 meters) or a 10BASE-T line (up to 185 meters). Supports either wired or fiber-optic Ethernet –XUP board only supports wired connection Built-in LED drivers –Allow easy connection of status LEDs to transceiver Two control options –MII (Media Independent Interface) for control by a MAC (Media Access Controller) Set of control registers and protocol for accessing them –Hardware Control (signal pins)

Lecture 1314 Block Diagram

Lecture 1315 Some Detailed Features OSP: Optimal Signal Processing –mixed-signal processing in improved receiver noise and cross-talk performance. –less computational logic than traditional DSP-based designs. When operating at 100 Mbps, the LXT972A continuously transmits and receives MLT3 symbols. –when not transmitting data, the LXT972A generates “IDLE” symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. –when no data is being exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link up. The LXT972A provides both an MDIO interface and a Hardware Control Interface for device configuration and management. –supports the IEEE MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT972A. –provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface uses the three LED driver pins to set device configuration.

Lecture 1316 Initialization Sequence

Lecture 1317 Some Details on Initialization On power-up or hardware reset the LXT972A reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using either Hardware Control or MDIO Control: –Force network link operation to: 100BASE-TX, Full-Duplex 100BASE-TX, Half-Duplex 10BASE-T, Full-Duplex 10BASE-T, Half-Duplex –Allow auto-negotiation/parallel-detection When the network link is forced to a specific configuration, the LXT972A immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT972A begins the auto-negotiation/parallel-detection operation.

Lecture 1318 Link Establishment Overview

Lecture 1319 Connectivity to the LXT972A MDC: Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 8 MHz.

Lecture 1320 Interfaces MDIO, MDC: MDIO management data line and clock line COLLISION: Collision Detected –The LXT972A asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the same time. CARRIER_SENSE: Carrier Sense –For 100BASE-TX links, a start-of-stream delimiter (SSD) causes assertion of carrier sense (CRS). –An end-of-stream delimiter (ESD) causes de-assertion of CRS.

Lecture 1321 Interfaces II RX_CLK: Clock for incoming data and control signals –Use this clock to latch incoming data –Will need to synchronize latched data to main system clock RX_DV: Indicates valid incoming data RX_ER: Invalid (error) data received from Ethernet RXD0-3: Bus for received data –Normal operation: 4 bits of data at a time –Hardware may support a 5-bit (Symbol) mode

Lecture 1322 Interfaces III TX_CLK: Clock for sending data to the chip –Again, not synchronized to system clock –An output of Ethernet transceiver TX_EN: Valid data being transmitted –Drive this high continuously from first to last nibbles of a packet TX_ER: Transmission error detected by transceiver TXD0-3: Data to transmit –Again, some support 4- or 5-bit format

Lecture 1323 Device Identifier Many devices require unique identifier, so-called “silicon serial number” Example would be Ethernet 48-bit MAC address Minimum number of wires should be dedicated to the infrequent access, ideally one (1-Wire Protocol) Concept: manipulating a single line precisely in time, a user can activate, program, or read back a ROM

Lecture 1324 The DS2401 enhanced Silicon Serial Number is a low-cost, electronic registration number that provides an absolutely unique identity. The DS2401 consists of a factory-lasered, 64-bit ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8- bit Family Code (01h). Data is transferred serially via the 1-Wire® protocol that requires only a single data lead and a ground return. Power for reading and writing the device is derived from the data line itself with no need for an external power source. XUP boards have such a 64-bit, factory electronic registration number. Dallas Semiconductor DS2401

Lecture 1325 Next Time Final project kickoff