Radiation Tolerant Source Interface Unit for the ALICE Experiment E. Dénes et al. LECC 2005 12- 16 September 2005, Heidelberg.

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Presentation transcript:

Radiation Tolerant Source Interface Unit for the ALICE Experiment E. Dénes et al. LECC September 2005, Heidelberg

September 2005LECC 2005, Heidelberg2 Outline Introduction Introduction DLL Radtol Project DLL Radtol Project Component test Component test FPGA tests FPGA tests Actel SIU tests Actel SIU tests Radtol SIU status Radtol SIU status Conclusions Conclusions

September 2005LECC 2005, Heidelberg3 Introduction: ALICE DAQ HLT Farm H-RORC FEP D-RORC LDC D-RORC LDC DIU SIU Event Building Network Readout Electronics Detector D-RORC LDC DIU SIU Readout Electronics Detector DIU SIU DIU SIU Source Interface Unit Duplex, multimode optical fiber Destination Interface Unit DAQ Readout Receiver Card Local Data Concentrator Detector Data Link GDC Global Data Collector 123 DDLs 262 DDLs 10 DDLs

September 2005LECC 2005, Heidelberg4 Introduction: Detector Data Link Simple, yet efficient standard interface between the detectors and the data-acquisition system Simple, yet efficient standard interface between the detectors and the data-acquisition system – User provided clock signal; flexible readout speed – Simple FIFO-like front-end interface – Data-push architecture – Full-duplex flow control Bi-directional, high-speed optical link Bi-directional, high-speed optical link – Sustained data rate up to 200 MB/s – Backward channel (towards the detectors) supports front- end electronics control or bulk download Radiation tolerant Source Interface Unit Radiation tolerant Source Interface Unit

September 2005LECC 2005, Heidelberg5 Radiation Levels in ALICE Detector Dose [rad / Gy] n- Φ [n x cm -2 ] n- Φ [cm -2 ] 1 MeV n-equ. h- Φ [cm -2 ] 1 MeV n-equ TPC (inner) 1600 / x x x TPC (outer) 220 / x x x TRD 180 / x x x TOF 120 / x x x HMPID/PHOS 50 / x x Detectors listed have the SIU’s directly installed on the front- end electronics Detectors listed have the SIU’s directly installed on the front- end electronics The other detectors have the SIU’s in shoeboxes close to TPC or in racks in the UX area or in one of the counting rooms The other detectors have the SIU’s in shoeboxes close to TPC or in racks in the UX area or in one of the counting rooms

September 2005LECC 2005, Heidelberg6 DDL Radtol Project Collaboration between CERN, RMKI - KFKI and its partners in Hungary (Cerntech, TU Budapest) Collaboration between CERN, RMKI - KFKI and its partners in Hungary (Cerntech, TU Budapest) Several tests were carried out to test components that were going to be used on the DDL SIU card Several tests were carried out to test components that were going to be used on the DDL SIU card Several reports and publications have been presented Several reports and publications have been presented Further tests of the SIU cards are being performed Further tests of the SIU cards are being performed

September 2005LECC 2005, Heidelberg7 SIU Components PLDSERDES Optical Transceiver Data path (Serial) Data path (2x16 bits) + control FEE interface Power monitor Power Regulator Power Xtal ID prom TXCLK RXCLK TXCLK Data path (32 bits) + control

September 2005LECC 2005, Heidelberg8 Components Tests (1/2) Crystal oscillators Crystal oscillators – Four oscillators from four manufacturers (Pletronics, Saronix, CFP, Ecliptek) have been passed the test TID: 100 krad (req. 5 krad) TID: 100 krad (req. 5 krad) Neutron: n/cm 2 (req. 4x10 11 ) Neutron: n/cm 2 (req. 4x10 11 ) Voltage regulators Voltage regulators – Two different device family have been tested TID: 100 krad (req. 5 krad) TID: 100 krad (req. 5 krad) Neutron: n/cm 2 (req. 4x10 11 ) Neutron: n/cm 2 (req. 4x10 11 ) – Micrel’s MIC5209 family (1.8V and 2.5V) failed – Linear Technology’s LT1963 family (1.8V and 2.5V) passed

September 2005LECC 2005, Heidelberg9 Components Tests (2/2) SERDES SERDES – TI TLK 2501 have been passed the tests Neutron: n/cm 2 (req. 4x10 11 ) Neutron: n/cm 2 (req. 4x10 11 ) Optical transceivers Optical transceivers – Two different device family (Agilent HFBR5910E and Infineon V23818-K305-L57) have been passed the tests TID: 22.8 krad (req. 5 krad) TID: 22.8 krad (req. 5 krad) Neutron: n/cm 2 (>20 yrs of ALICE) Neutron: n/cm 2 (>20 yrs of ALICE) – Gbps SFP ( HFBR5720L and V23818-M305-B57 ) version of those transceivers were tested as part of the DDL prototype card TID: tested up to 10 krad (no damage) TID: tested up to 10 krad (no damage) SEU: Only a few errors may be accounted to the optical transceivers when tested with neutrons up to n/cm 2 SEU: Only a few errors may be accounted to the optical transceivers when tested with neutrons up to n/cm 2

September 2005LECC 2005, Heidelberg10 SRAM-based FPGA Tests Earlier tests show that the required TID values are tolerated Earlier tests show that the required TID values are tolerated Many experiences show that SRAM-based devices are sensitive to SEU effects Many experiences show that SRAM-based devices are sensitive to SEU effects Two SRAM-based FPGA devices have been tested Altera APEX-E device (EP20K60E, used on SIU prototypes) was tested with p and n in 2003 Altera APEX-E device (EP20K60E, used on SIU prototypes) was tested with p and n in 2003 – Embedded memory test – Logic cell test Xilinx Virtex II device was tested with p in 2004 Xilinx Virtex II device was tested with p in 2004 – Logic cell test Special test firmware and software has been developed to capture SEU induced bit errors and configuration loss

September 2005LECC 2005, Heidelberg11 Results of the FPGA Tests Beam type ProtonNeutron Energy [MeV] – 14 Test Logic Cell Memory Cell Logic Cell Memory Cell σ [ cm 2 /bit] 7.08 ± ± ± ± ± ± ± ± Beam type Proton Energy [MeV] Test Logic Cell σ [ cm 2 /bit] 6.75 ± ± ± 2.6 Altera APEX-E test results Xilinx Virtex II test results

September 2005LECC 2005, Heidelberg12 Consequences Prototype DDL cards FPGA: Altera APEX-E (EP20K60E, 160 kgates  m) FPGA: Altera APEX-E (EP20K60E, 160 kgates  m) Amongst all consequences of radiation, one is really problematic: the loss (or corruption) of the device configuration (= configuration cell changes its state due to high-energy particle interacting with the device) Amongst all consequences of radiation, one is really problematic: the loss (or corruption) of the device configuration (= configuration cell changes its state due to high-energy particle interacting with the device) Radiation tests have shown that we should expect 1 loss of configuration in 1 of the 400 DDL SIUs every hour Radiation tests have shown that we should expect 1 loss of configuration in 1 of the 400 DDL SIUs every hour New DDL card is needed 4 different solutions have been discussed (Altera Cyclon, Xilinx Virtex, Actel ProASIC+, Custom ASIC) 4 different solutions have been discussed (Altera Cyclon, Xilinx Virtex, Actel ProASIC+, Custom ASIC) The one based on Actel ProASIC+ has been selected The one based on Actel ProASIC+ has been selected – 0.22  m flash-based CMOS process

September 2005LECC 2005, Heidelberg13 Actel ProASIC+ Bright side Irradiation tests are encouraging Irradiation tests are encouraging Capacity: no problem to fit the DDL SIU in. (PQFP 208 pins 75k to 1Mgates) Capacity: no problem to fit the DDL SIU in. (PQFP 208 pins 75k to 1Mgates) Lower power consumption Lower power consumption Instant-on device (no configuration at power-on) Instant-on device (no configuration at power-on) No external device needed for storing the configuration No external device needed for storing the configuration Not so bright… Lot of design work was needed because of different architecture Lot of design work was needed because of different architecture – Learn the peculiarities of the Actel software tools – Timing-critical modules to be re-engineered 110 MHz) – Less internal resources (e.g. high-speed global network) – Less complex logic elements Special voltage (+16 V and V) required to reload configuration Special voltage (+16 V and V) required to reload configuration – remote configuration is not supported

September 2005LECC 2005, Heidelberg14 Radtol SIU Block Diagram Actel APA150 TI TLK2501 Agilent HFBR-5720L Data path (Serial) Data path (2x16 bits) + control FEE interface MHz +3.3V LVTTL 2125 Mbps LVPECL 50 MHz +3.3V LVTTL Power monitor 2.5V +3.3V Xtal ID prom TXCLK RXCLK Data path (32 bits) + control 2125 MBd 850 nm optical Optical interface RXCLK TXCLK Notes: PCB design is compatible for APA150 (ProASIC+) and A3P250 (ProASIC3) devices PCB design is compatible for APA150 (ProASIC+) and A3P250 (ProASIC3) devices Four prototype boards have been manufactured Four prototype boards have been manufactured

September 2005LECC 2005, Heidelberg15 Radtol SIU Firmware ACTEL APA 150 version Modules have been ported from the ALTERA DDL firmware Modules have been ported from the ALTERA DDL firmware Timing critical modules have been reengineered and optimized Timing critical modules have been reengineered and optimized Complete firmware is being simulated and then tested on real hardware Complete firmware is being simulated and then tested on real hardware DDL transactions are being tested using the RORC utilities (both in CERN and in RMKI-KFKI, Budapest) DDL transactions are being tested using the RORC utilities (both in CERN and in RMKI-KFKI, Budapest) Long term tests are being executed using DATE Long term tests are being executed using DATE

September 2005LECC 2005, Heidelberg16 Actel ProASIC+ Test Results (1/2) May 2004, TSL, Uppsala, Sweden Tests were done using the evaluation board (APA075) Tests were done using the evaluation board (APA075) Proton 171, 94 and 48 MeV Proton 171, 94 and 48 MeV No configuration loss No configuration loss June 2004, ATOMKI, Debrecen, Hungary Tests were done using the evaluation board (APA075) Tests were done using the evaluation board (APA075) TID tests with Co 60, dose rate of approx. 20 krad/h TID tests with Co 60, dose rate of approx. 20 krad/h No problem up to 12 krad, when the device stopped functioning No problem up to 12 krad, when the device stopped functioning After 1 hour at room temperature the device started to work (annealing) After 1 hour at room temperature the device started to work (annealing) March 2005, ATOMKI, Debrecen, Hungary Tests were done using both the evaluation board and the new SIU (APA150) Tests were done using both the evaluation board and the new SIU (APA150) Neutron beam with the energy < 15 MeV Neutron beam with the energy < 15 MeV No errors have been detected on the evaluation board (5*10 10 n/cm 2 ) No errors have been detected on the evaluation board (5*10 10 n/cm 2 ) One error on the SIU provoked link down after the equivalent of 5 yrs (10 11 n/cm 2 ). It could be fixed by cycling the power of the card One error on the SIU provoked link down after the equivalent of 5 yrs (10 11 n/cm 2 ). It could be fixed by cycling the power of the card

September 2005LECC 2005, Heidelberg17 Actel ProASIC+ Test Results (2/2) May 2005, ATOMKI, Debrecen, Hungary, Neutron beam with the energy < 15 MeV Tests were done using the new SIU; short data block were circulated through the loop-back implemented in the SIU firmware Tests were done using the new SIU; short data block were circulated through the loop-back implemented in the SIU firmware Neutron beam with the energy < 15 MeV Neutron beam with the energy < 15 MeV Few errors have been detected; during initialization the SIU stuck in power-on reset state (link initialization error has been fixed remotely) Few errors have been detected; during initialization the SIU stuck in power-on reset state (link initialization error has been fixed remotely) May 2005, TSL, Uppsala, Sweden, Neutron beam with energy 95 MeV Combined test of the TPC Readout Electronics (FECs + RCU) and the new SIU performed by the TPC group Combined test of the TPC Readout Electronics (FECs + RCU) and the new SIU performed by the TPC group SIU contribution to transmission errors: 0 (preliminary) SIU contribution to transmission errors: 0 (preliminary) June 2005, ATOMKI, Debrecen, Hungary, Neutron beam with the energy < 15 MeV Tests were done using the new SIU; long data block were received from FEE emulator and send to DIU and RORC Tests were done using the new SIU; long data block were received from FEE emulator and send to DIU and RORC Data errors have been detected; tests have shown that we should expect 1 bit error every 4 hour in the DAQ system containing 400 DDL SIUs Data errors have been detected; tests have shown that we should expect 1 bit error every 4 hour in the DAQ system containing 400 DDL SIUs

September 2005LECC 2005, Heidelberg18 Project Status Prototype boards have been manufactured Prototype boards have been manufactured Firmware is extensively tested using the RORC utilities (both in CERN and in RMKI - KFKI, Budapest) Firmware is extensively tested using the RORC utilities (both in CERN and in RMKI - KFKI, Budapest) Long term tests are being executed using DATE Long term tests are being executed using DATE Many radiation tolerance test have been made, results are promising Many radiation tolerance test have been made, results are promising Production Readiness Review (PRR) successfully held in June Production Readiness Review (PRR) successfully held in June Tests recommended by the PRR referees has been started Tests recommended by the PRR referees has been started ACTEL released the ProASIC3 device, test board ordered ACTEL released the ProASIC3 device, test board ordered Everything is prepared for series production Everything is prepared for series production

September 2005LECC 2005, Heidelberg19 The Future Actel ProASIC3 (3 rd generation) Actel ProASIC3 (3 rd generation) – Pin compatible with existing ProASIC+ devices – Higher performance, lower power consumption – Improved global network supporting up to 18 global signals We continue the radiation tolerant tests We continue the radiation tolerant tests – To find out the reason of data errors SEU produced in memory or register cells? SEU produced in memory or register cells? Special test firmware developed Special test firmware developed – Develop error correcting firmware We continue tests recommended by the PRR referees We continue tests recommended by the PRR referees 12 DDLs for TPC tests at Point 2 will be available in October 12 DDLs for TPC tests at Point 2 will be available in October

Thank you!