KEK High Energy Accelerator Research Organization Katsuro Nakamura (KEK) T. Bergauer B, G. Casarosa F, M. Friedl B, K. Hara, T. Higuchi A, C. Irmler B, R. Itoh, T. Konno G, Z. Liu E, M. Nakao, Z. Natkaniec C, W. Ostrowicz C, E. Paoloni F, M. Schnell D, S.Y. Suzuki, R. Thalmeier B, T. Tsuboyama, S. Yamada, H. Yin B KEK 、 Kavli IPMU (WPI) A 、 HEPHY B 、 IFJ C 、 Univ. of Bonn D 、 IHEP E, INFN Pisa F, Tokyo Metropolitan Univ G. TIPP2014 (June 6, 2014) Silicon-Strip Vertex Detector (SVD) for Belle II experiment 6/ 6/20141 TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 4-layer DSSD sensors –measure 2D track position for charged particles –more than 220,000 readout strips SVD provides RoI (region of interest) in the inner 2-layer Silicon-Pixel Vertex Detector (PXD) –PXD data reduction and accurate track reconstruction charged particle Silicon-Strip Vertex Detector (SVD) Belle II detector KEK 6/ 6/20142 DSSD TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) APV25 chip –Front-end electronics for DSSD signal readout –Provides 128-channels analog signals sampled among several clock ticks –Shaping time: 50 nsec –Suitable for high occupancy in Belle II SVD 6- and 3-samples/trigger modes will be used for Belle II SVD –6-samples/trigger is preferable for good peak finding Requirements on triggers from APV25 –Maximum trigger rate: (140 clocks/sample) 38kHz (6-samples), 76kHz (3-samples) –cf. max. trigger rate in Belle II is 30kHz –Minimum trigger interval: (3 clocks/3-samples) 189nsec (6-samples), 94nsec (3-samples) –Maximum trigger latency: 5.0 usec (available pipe-line size of 160 samples) 6/ 6/ APV25 chip clock tick (32MHz) ADC output from APV25 (6 samples/trigger) 1 sample a particle hit discussed later ✔ ✔ ✔ ✔ TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) control signals Performance of the readout system has to be confirmed with prototypes before final production. FADC x48 FTB x48 flash ADC zero-sup. data format data format B2L Aurora basf2 Belle II DAQ HSLB DAQ PXD system PXD RoI data flow belle2link Aurora link Belle II SVD Buffer x4 FADC-Ctrl B2TT decoder APV Trig. Gen. copper cables FADC control VME backplane clock, trigger, reset … clock, trigger, reset … belle2tt 1748 APV25’s ~2m copper cables Junction boxes ( signal repeater ) ~10m copper cables 6/ 6/2014 TIPP2014, Amsterdam 4 clock, trigger, reset … SVD readout system APV25 chips calculate RoI on-line Belle II trigger/ timing controller SVD readout system is driven by 32MHz clock.

KEK (High Energy Accelerator Research Organization) High signal density –readout 48 APV25 outputs APV25 signal processing on FADC –analog level conversion (AC coupling) –10-bit ADC –FPGA (Stratix IV) data processing FIR filter Common-Mode Correction Zero-Suppression –data transmission to FTB 6/ 6/20145 prototype FADC board signals from 48 x APV25 FTB board VME 9U TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 6/ 6/20146 (6-samples/trigger) TIPP2014, Amsterdam CMC distribution (n-side) hit information from APV25 chip average of ADC shifts from pedestal  Common-Mode Correction ADC distribution before CMC ADC distribution after CMC typical MIP: 70 ADC typical MIP: 70 ADC [ADC] ADC Clock Ticks (32MHz) obtained from raw ADC data obtained from raw ADC data after CMC

KEK (High Energy Accelerator Research Organization) FTB connect SFP ports each other 76/ 6/2014 SFP port FPGA Xilinx SPARTAN-6 SC signal receiver SFP port JTAG port data from FADC DAQ PXD Stability test for serial lines with PRBS-7 prototype FTB board VME 3U TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) control signals FADC x48 FTB x48 flash ADC zero-sup. data format data format B2L Aurora basf2 Belle II DAQ HSLB DAQ PXD system PXD RoI data flow belle2link Aurora link Belle II SVD Buffer x4 FADC-Ctrl B2TT decoder APV Trig. Gen. copper cables FADC control VME backplane FTSW clock, trigger, reset … clock, trigger, reset … belle2tt 1748 APV25’s ~2m copper cables Junction boxes ( signal repeater ) ~10m copper cables 6/ 6/2014 TIPP2014, Amsterdam 8 clock, trigger, reset … SVD readout system APV25 chips reduction of PXD data size trigger/ timing distributer

KEK (High Energy Accelerator Research Organization) 6/ 6/20149 Superconducting solenoid magnet APV25 chips 4-layer test SVD modules DSSD sensor in light-shielding box (max. 1T) test SVD modules TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 6/ 6/2014 TIPP2014, Amsterdam 10 Belle II DAQ setup PXD-DatCon system FADC board JTAG server FTB board same readout chain as Belle II experiment –first test of the full readout chain trigger rate: ~ 400 Hz confirmation of correct data processing –event number check –CRC checksum Stable operation of the readout during the beam test (about 3 weeks) Stable operation of the readout during the beam test (about 3 weeks) SVD readout system

KEK (High Energy Accelerator Research Organization) 6/ 6/ event display w/ magnetic field SVD modules reconstructed track cluster hit efficiency for tracks TIPP2014, Amsterdam observed performance of SVD module cluster charge distributioncluster size distribution position of track projection [cm] cluster hit efficiency for tracks efficiency: 99.4% efficiency

KEK (High Energy Accelerator Research Organization) 12 Implement ‘ APV25-FIFO emulator ’ 6/ 6/2014 TIPP2014, Amsterdam APV25 chips Belle II SVD Belle II trigger/timing controller module: global decision of Level-1 trigger accept trigger signals to all sub-systems APV25 trigger-FIFO 32 samples FIFO occupancy APV25-FIFO emulator 32 samples emulated FIFO occupancy threshold for trigger veto global trigger decision veto emulated

KEK (High Energy Accelerator Research Organization) 13 threshold: 26 samples no trigger/busy propagation trigger interval: 190nsec (24 clocks) Trigger dead time vs. Raw trigger rate (Simulation) Belle II designed max. trigger rate only 6-samples only 3-samples 6/ 6/2014 TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 6/ 6/ Schedule TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 6/ 6/ TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 6/ 6/ TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) Trigger rate –1 sample data transmission to FADC takes 140 clock cycles. –3-sample mode  Maximum trigger rate is 76kHz –6-sample mode  Maximum trigger rate is 38kHz cf. The target trigger rate in Belle II is 30kHz. –6-sample mode works fine in low luminosity, but combination of 3- and 6-samples have to be used in higher luminosity. Minimum trigger interval –1 trigger reception needs 3 clock cycles for 3-sample mode and 6 clock cycles for 6- sample mode. –3-sample mode  Minimum trigger interval is ~94 nsec. –6-sample mode  Minimum trigger interval is ~190 nsec. CDC also requires 200 nsec separation. Maximum trigger latency –Maximum available pipeline depth is 160 clock cycles. –That requires trigger latency of less than 5 usec. APV25 has FIFO with 32-samples depth –To avoid FIFO overflow, a finite trigger-dead-time has to be introduced. 6/ 6/ TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization)  Supply HV and LV to DSSD and APV25.  DC/DC converter  Joint signals between APV25 and FADC board. 6/ 6/ prototypes for p- and n-sides DC/DC converters TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) Modes of operation: –Raw mode raw ADC data for a defined length –Transparent mode APV25 frame detection with header data and raw data of all strips –Zero-suppressed mode Pedestal subtraction, CMC, only hits above threshold (3 or 6 samples) –Zero-suppressed/hit time finding mode (not implemented yet) Peak sample and peak time, all 3 or 6 samples only for unclear cases (such as double peak = pileup) Raw + transparent are typically used SVD-internally (timing adjustments, pedestal/noise evaluation, calibration, …) Zero-suppressed (+hit time finding) are the normal data formats for physics data acquisition 6/ 6/ TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) selector All the three data-modes are working well. 6/ 6/ ADC data decoder APV frame detection data reordering RAW data pipeline 512 cells RAW data pipeline 512 cells CMC 1 CMC 2 Hit finder & encoder zero suppressed data zero suppressed data encoder transparent data transparent data encoder raw mode data raw mode data Data Transmitter for FTB ADC data of APV output ADC data of APV output FIFO x 48 APVs TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) Error status of FADC is important to guarantee the data correctness. The most probable error sources in firmware: 6/ 6/ APV FIFO full 32sample depth FIFO full 2k word depth ADC frame detection error APV header detection error TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) Error-bits for the quality confirmation and diagnoses. 22 new format for the beam test (from Jan. 21, 2014) old format 6/ 6/2014 TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) The current data format works well. A few improvements will be applied in future. –Confusing magic numbers in header and trailer will be changed. Currently, they are same as the magic numbers in B2L header and trailer. –Trailing ‘0’ in the MSB 8-bits to distinguish all types of frames. –Leave all the FADC data as they are. 23 Current formatNext format 6/ 6/2014 TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) We will have 4 crates with FADC modules One has single FADC-Controller –Receives FTSW signals –Distributes clock, trigger and other controls to all Buffer Each crate has single Buffer module –Receives FADC-Controller signals –Distributes signals to FADCs through backplane bus 1 st prototype of FADC-Controller board Buffer board FTSW 4 Buffer board FPGA STRATIX IV FPGA CYCLON II buffers GbE interface FADC-Controller board All FADC boards in a crate buffers 6/ 6/ TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 6/ 6/ particle signal calibration signal TuxDAQ hit map APV25 output TuxOA TuxDAQ + TuxOA –C++ application Linux 32/64 bit –Used at DESY beam test TuxDAQ –SVD standalone DAQ –Samples data on FADC data-stream noise data gain calibration data as well as physics data –Configures parameters in FADC system –ADC clock delay scan TuxOA –Simple analyses of sampled FADC data Noise and pedestal gain calibration constants –Hit profile (chip / module level) Worked well at DESY TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) PXD and IBBelle will employ EPICS, and SVD shares CO2 cooling system and environmental monitors with PXD  SVD will be involved in the EPICS control system. –Common data logging on EPICS database EPICS integration on our software needs to be done. 6/ 6/ Integration plan of SVD run/slow control SVD run control GUI SVD HV/LV control GUI TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 6/ 6/ SVD FWD SVD BWD TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) M. Friedl (HEPHY): System & schematics design, supervision S. Schmid (HEPHY): CAD schematics & PCB layout J. Pirker (HEPHY): Parts purchasing, assembly (soldering) M. Eichberger (HEPHY): Assembly (soldering, wire bonding) C. Irmler (HEPHY): Assembly (wire bonding), software supervision, Origami/hybrid testing R. Thalmeier (HEPHY): FADC hardware and firmware H. Yin (HEPHY): Online software W. Ostrowicz (Cracow): FTB hardware and firmware Z. Natkaniec (Cracow): FTB hardware and firmware M. Schnell (Bonn): FTB DatCon interface firmware K. Nakamura (KEK): Firmware, B2Link/B2TT, System integration at KEK 6/ 6/ TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 6/ 6/ % dead time Trigger dead time from the FTSW “pipeline busy” is simulated. Simulation with LFSR (linear feedback shift register) pattern generator, which is really used in FTSW, well describes the measured live ratios. –  There is no other big dead time sources in our system. Green curve shows expected live ratio with Poisson distribution triggers (real triggers) –Dead time is expected to be about 20% at 30kHz. Too large for the Belle II operation.  APV25 emulator would be necessary for our busy handling. TIPP2014, Amsterdam

KEK (High Energy Accelerator Research Organization) 30 p-side n-side NO. NAME VALUE ERROR SIZE DERIVATIVE 1 p e e e e-03 2 p e e e e-01 3 p e e e e-03 4 p e e e e-03 5 p e e e e-01 6 p e e e e-02 NO. NAME VALUE ERROR SIZE DERIVATIVE 1 p e e e e-02 2 p e e e e+00 3 p e e e e-01 4 p e e e e-02 5 p e e e e-01 6 p e e e e-02

KEK (High Energy Accelerator Research Organization) 31 red: # of extrapolations blue: # of associated clusters after previous cut (|x|<8*p2) division Efficiency is more than 99% in both p-side and n-side. (*) The red lines are not fitting results, but just result of division of entries. p-side n-side p-side n-side

KEK (High Energy Accelerator Research Organization) 32 p-side n-side CMC128CMC32 CMC16 CMC128CMC32 CMC16