Gheorghe M. Ştefan

Tristate buffers enable = 0, out = hi-z enable = 1, out = in’ Interconnecting two systems: en1=1, en2=0 : System 1 sends, System 2 receives en1=0, en2=1 : System 2 sends, System 1 receives en1=0, en2=0 : System 1 receives, System 2 receives en1=1, en2=1 : forbidden 2014Digital Integrated Circuits - week three2

Inverting & non-inverting tristate buffer 2014Digital Integrated Circuits - week three3

Transmission gate en = 1 => out = in en = 0 => out = hi-z Main limitation: R ON is serially connected to C L Main advantage: no connection to V DD and ground 2014Digital Integrated Circuits - week three4

Elementary inverting multiplexor Low power, small area, but low speed 2014Digital Integrated Circuits - week three5

Memory circuits Data latches revisited Delay flip-flop (DF-F) Reset-able DF-F 2014Digital Integrated Circuits - week three6

Data latches 0 : active level of CK 1 : active level of CK CK = 1 : loop closed CK = 1 : transparent CK = 0 : transparent CK = 0 : loop closed 2014Digital Integrated Circuits - week three7

The master-slave structure of DF-F What is the active edge of clock? How can the active edge be changed? 2014Digital Integrated Circuits - week three8

master-latch is transparent, slave-latch latches master-latch latches, slave-latch is transparent the overall structure is anytime non-transparent 2014Digital Integrated Circuits - week three9

Reset-able DF-F The free inverter is substituted by an appropriate gate Both, master-latch and slave–latch must be “forced” asynchronously 2014Digital Integrated Circuits - week three10

Growing – Speeding - Featuring Size vs. Complexity Time restrictions in digital systems Growing the size by composition Speeding by pipelining Featuring by closing new loops The taxonomy of digital systems 2014Digital Integrated Circuits - week four11

Size vs. Complexity Size: the dimension of physical resources – S digital_system Gate size: the number of CMOS pairs Area size: silicon area Depth: number of logic levels Complexity (algorithmic complexity): ~ the dimension of the shortest description C digital_system Simple circuit: C simple_system << S simple_system Complex circuit: C complex_system ~ S complex_system 2014Digital Integrated Circuits - week four12

Size vs. Complexity (examples) 2014Digital Integrated Circuits - week four13 Complex circuit: Simple circuit:

Time restrictions in digital systems 2014Digital Integrated Circuits - week four14 t in_reg : minimum input arrival time before clock t reg_reg : minimum period of clock = T clock_min = 1/f clock_max t in_out : maximum combinational delay path t reg_out : maximum required time after clock

Example 2014Digital Integrated Circuits - week four15 t in_reg = t p (adder) + t p (selector) + t su (register) = ( )ps t reg_reg = T clock_min = 1/f max = t p (register) + t p (adder) + t p (selector) + t su (register) = ( )ps f max = 1.21 GHz t in_out = t p (comparator) = 300ps t reg_out = t p (register) + t p (comparator) = ( )ps

Pipelined connections 2014Digital Integrated Circuits - week four16

Blocking – Non-Blocking assignment 2014Digital Integrated Circuits - week four17 Blocking assignment: “=“ for combinational circuits Non-blocking assignment: “<=“ for edge triggered transitions

Fully buffered connection 2014Digital Integrated Circuits - week four18 t in_reg = t su (regsiter) t reg_reg = t p (regsiter) + t p (comb) + t su (regsiter) = 1/f clock_max t in_out : not defined t reg_out = t p (regsiter)

Growing by composing 2014Digital Integrated Circuits - week four19 f(x) = g(h 1 (x), h 2 (x), … h m (x) )

Serial & Parallel Composition 2014Digital Integrated Circuits - week four20

Example: inner product 2014Digital Integrated Circuits - week four21

Example: inner product (cont.) 2014Digital Integrated Circuits - week four22

Speeding by pipelining With no pipeline: f clock = 1/(t reg +t f +t su ) = 1/(t reg +t h_1 +t g +t su ) Latency: λ = 2 With pipeline: f clock = 1/(t reg + max(t h_1 +t g )+t su ) Latency: λ = Digital Integrated Circuits - week four23

Example: pipelined inner product 2014Digital Integrated Circuits - week four24 t p (mult) = 2 ns t p (add) = 1ns t su (reg) = 20ps t p (reg) = 50ps No pipeline: f ck = GHz With pipeline: f ck = GHz

Home work 3 Problem 1: design at the gate level an asynchronously reset- able (RST) and preset-able (SET) DF-F. Problem 2: design a synchronously reset-able DF-F. Problem 3: design the test module for the pipelined version of the inner product circuit represented in Figure 3.6 and described in Example 3.7. Use it to simulate the inner product circuit. 2014Digital Integrated Circuits - week three25