Avshalom Elyada, Ran GinosarPipeline Synchronization 1 A Unique and Successfully Implemented Approach to the Synchronization Problem Based on the article “Pipeline Synchronization” by Jakov N. Seizovic, 1994

Avshalom Elyada, Ran GinosarPipeline Synchronization 2 Search for New Solutions More and more sync operations per unit time: –complex chips  more inter-domain transitions –Higher freq  less settling time  smaller MTBF Existing solutions no longer deliver required PoF –And if they can it is a matter of the next generation or two… inter-domain interfaces are often long interconnects; need to solve both with one mechanism

Avshalom Elyada, Ran GinosarPipeline Synchronization 3 Current Solutions Reviewed in previous lectures –Two-flop –Clock shifting/streching, predicitve –… All treat sync as “one-shot” process, at end of which signal is either synced or not

Avshalom Elyada, Ran GinosarPipeline Synchronization 4 Pipeline approach: control signals synced in stages, along with data flow Each step of the pipeline “partially synchronizes” the signal, reducing it’s degree of asynchronicity. More stages  less PoF: safety vs. latency tradeoff Data is latched at each stage –Divide long interconnect into short segments –Deal with inter-bit skew

Avshalom Elyada, Ran GinosarPipeline Synchronization 5 Degree of Asynchronicity Until now, signal was either synchronous or asynchronous For sync in stages, let’s look at more information: –A signal’s arrival time in interval [0-T] as random variable with distribution function –  and degree of asynchronicity :

Avshalom Elyada, Ran GinosarPipeline Synchronization 6 For a time-window 0<T w <T, Asynchronicity of a signal is defined as: Intuitive meaning: when sampling within a window of T hold +T setup =T w, A s is the lowest prob. of MS behavior that can be achieved. Asynchronicity of Signals

Avshalom Elyada, Ran GinosarPipeline Synchronization 7 Insightful Examples Synchronous: can make A s = 0 if satisfy T hold +T setup < certain T max Asynchronous: A s = T w /T A s = 1 corresponds to a “Malicious” signal: no matter where we sample, the signal always arrives within our time window

Avshalom Elyada, Ran GinosarPipeline Synchronization 8 Building blocks –Stage-synchronizer based on one or two Mutual-Exclusion elements –FIFO element Start with async elements (latch & latch-like) –Explore possible use of DFFs for both data & sync (ctrl) path More appealing to sync. designers

Avshalom Elyada, Ran GinosarPipeline Synchronization 9 An ME as a Synchronizer (I) Outputs mutually exclusive : only one asserts at a given time Connect ‘clk’ and signal ‘R’ to inputs ‘A’ synced output, other output unused clk S X R1R1 R0R0 A1A1 A0A0 ME RA

Avshalom Elyada, Ran GinosarPipeline Synchronization 10 An ME as a Synchronizer (II) A  is synced to clk 

Avshalom Elyada, Ran GinosarPipeline Synchronization 11 An ME as a Synchronizer (III) Inverse the clk: A  syncs to clk   sync to posedge R1R1 R0R0 A1A1 A0A0 ME RA clk

Avshalom Elyada, Ran GinosarPipeline Synchronization 12 ME Implementation A latch with a MS filter As inherent to any sync. decision h/w, ME has a MS-state. –If in MS-state, Ao does not assert until MS resolved –Next clk edge forces ME out of MS-state.

Avshalom Elyada, Ran GinosarPipeline Synchronization 13 Dual-edge Synchronizer Want to use 2- phase protocol, better for long interconnects Need to sync rise and fall of R i ->R o Use 2 MEs and another latch

Avshalom Elyada, Ran GinosarPipeline Synchronization 14 FIFO Element Holds data in stage while ctrl is synced 2-phase single-rail handshake –2-phase more suited for long interconnects Latch as mem. element –can also use DFF, appeal to sync. designers Simple async ctrl (petrify) –More on implementation next time…

Avshalom Elyada, Ran GinosarPipeline Synchronization 15 Pipeline w/ Embedded Synchronizing S Ri Ai Di Ro Ao Do S Ri Ai Di Ro Ao Do S Ri Ai Di Ro Ao Do    SynchronousAsynchronous   Taken from “Synchronization Ideas”, Charles E. Dike, Intel Corporation

Avshalom Elyada, Ran GinosarPipeline Synchronization 16 Likewise for Multi- Synchronous Domains S Ri Ai Di Ro Ao Do S Ri Ai Di Ro Ao Do Ri Ai Di Ro Ao Do S    Mult.-sync. domain B Mult.-sync. domain A  S  S  S Taken from “Synchronization Ideas”, Charles E. Dike, Intel Corporation

Avshalom Elyada, Ran GinosarPipeline Synchronization 17 Step-by-Step

Avshalom Elyada, Ran GinosarPipeline Synchronization 18 Long Interconnect: Pipeline Synchronizer Seizovic, “Pipeline Synchronization,” Async 1994 Kessels, Peeters, Kim, "Bridging Clock Domains by synchronizing the mice in the mousetrap", PATMOS, 2003 B clk half cycle distance Last 3 stages in each direction contain synchronizers A clk MEME MEME REQ MEME B clk MEME MEME ACK MEME

Avshalom Elyada, Ran GinosarPipeline Synchronization 19 Probability of Failure Pipeline PoF as formally proven in article: -k(T/2-T oh )/τ P k =P 0 *e –P 0 – PoF without any sync –k– # stages t = T/2-T oh is the time each sync has T oh = synchronizer+FIFO delay Recall prob. of exit MS is P(t) = exp(-t/τ) Intuitively, each stage works alone during its allocated time (while clk is high, minus overhead). The contributions are combined.

Avshalom Elyada, Ran GinosarPipeline Synchronization 20 Future At each stage, time for sync is T/2 –Toh. Insert logic in the pipeline –On data, no problem –On ctrl possible, Toh effectively grows  need more stages for same PoF –But pipeline would have added functionality Can also contemplate insertion of ME-elements along existing pipelines in synchronous designs…

Avshalom Elyada, Ran GinosarPipeline Synchronization 21 Glancing Back Need for better solution that also addresses long-interconnect issue Asynchronicity (degree of) Syncing in stages: pipeline ME as a synchronizer FIFO element Pipeline Synchronizers

Avshalom Elyada, Ran GinosarPipeline Synchronization 22 Next Presentation More on Pipeline Sync, … “Bridging Clock Domains by Synchronizing the Mice in the Mousetrap” Kessels, Peeters, Kim Philips Research Laboratory, 2003