External Interrupt Module MTT EXTERNAL INTERRUPT REQUEST MODULE (IRQ)

External Interrupt Module MTT Module Objective By the end of this module, you should be able to: Enable/disable IRQ interrupts Configure the trigger sensitivity Acknowledge the interrupts Configure port external interrupts

External Interrupt Module MTT EXTERNAL INTERRUPT (IRQ) MODULE 68HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable Memory (EPROM) LVI COP Monitor ROM IRQ BREAK RESET Supports external interrupt functions Two dedicated external interrupt pins IRQ1/Vpp and IRQ2 Individually programmable Separate interrupt masks IRQ2 Interrupt Disable Configurable Port as external interrupts Allows additional external interrupts

External Interrupt Module MTT Global Interrupt Mask Code Condition Register (CCR) Global CPU interrupt disable mask 1 = All CPU interrupts are disabled SWI interrupt is non-maskable 0 = CPU interrupts are processed RESET:x11x1xxx WRITE: READ: CCR V 1 1HI N C Z

External Interrupt Module MTT FROM RESET I BIT SET? FETCH NEXT YES NO INTERRUPT? INSTRUCTION. SWI INSTRUCTION? RTI INSTRUCTION? NO STACK CPU REGISTERS. NO SET I BIT. LOAD PC WITH INTERRUPT VECTOR. NO YES UNSTACK CPU REGISTERS. EXECUTE INSTRUCTION. YES IRQ Interrupt Flowchart

External Interrupt Module MTT IRQ1 Block Diagram ACK1 IMASK1 D Q CK CLR IRQ1 INTERRUPT REQUEST HIGH VOLTAGE DETECT TO MODE SELECT LOGIC IRQ1 LATCH IRQ1/V pp V DD MODE1 SYNCHRO- NIZER

External Interrupt Module MTT IRQ1 Interrupt request is latched on falling edge Trigger may be edge sensitive only or level and edge sensitive Maskable through IMASK1 bit CPU automatically clears request during interrupt processing Software may optionally clear the request Vector address is $FFFA and $FFFB (68HC708XL36)

External Interrupt Module MTT IRQ1 Control IRQ Status and Control Register (ISCR) IRQ1 edge/level select (MODE1) –Selects trigger sensitivity of the IRQ1 pin 1 = Interrupt requests on falling edges or low levels 0 = Interrupt requests on falling edges only IRQ1 Interrupt Mask (IMASK1) 1 = IRQ1 Interrupts requests disabled 0 = IRQ1 Interrupts requests enabled IRQ1 Interrupt request acknowledge (ACK1): write-only –Used to Clear the IRQ1 request Writing logic 1 clears the IRQ latch –Always reads as logic zero. RESET: WRITE: ACK2 ACK1 READ: 0 0 ISCR PIN2IMASK2MODE2IRQ2DISIMASK1MODE1

External Interrupt Module MTT IRQ2/ KEYBOARD INTERRUPT IRQ2 ACK2 DQ CK CLR V DD MODE2 SYNCHRO- NIZER IMASK2 PIN2 IRQ2DIS IRQ2/KEYBOARD INTERRUPT LATCH REQUEST IRQ2 Block Diagram CONFIGURABLE PORT PINS

External Interrupt Module MTT IRQ2 Interrupt request is latched on falling edge Trigger may be edge sensitive only or level and edge sensitive Maskable through the IMASK2 bit CPU automatically clears request during interrupt processing Software may optionally clear the request Vector address is $FFE0 and $FFE1 (68HC708XL36)

External Interrupt Module MTT IRQ Status and Control Register (ISCR) IRQ2/Keyboard Interrupt edge/level select (MODE2) –Selects trigger sensitivity of the IRQ2 and Keyboard Interrupt Pins 1 = Interrupt on falling edges or low levels 0 = Interrupt on falling edges only IRQ2/Keyboard Interrupt Mask (IMASK2) 1 = IRQ2 and Keyboard Interrupts disabled 0 = IRQ2 and Keyboard Interrupts enabled IRQ2/Keyboard Interrupt request acknowledge (ACK2) –Used to Clear the IRQ2/Keyboard requests Writing logic 1 acknowledges the request –ACK2 always reads as logic zero IRQ2 Pin Interrupt Latch Disable (IRQ2DIS) –Prevents the IRQ2 pin from latching interrupt requests into the IRQ2/Keyboard interrupt latch 1 = IRQ2 pin interrupt requests not latched 0 = IRQ2 pin interrupt requests latched IRQ2 Control IRQ2 Pin state (PIN2) –Reflects the current level of the IRQ2 pin –Can be used to distinguish between Port interrupt and an actual IRQ2 interrupt 1 = IRQ2 pin at logic one 0 = IRQ2 pin at logic zero RESET: WRITE: ACK2 ACK1 READ: 0 0 ISCR PIN2IMASK2MODE2IRQ2DISIMASK1MODE1

External Interrupt Module MTT KB0IE TO PTD0 PULL-UP ENABLE KB7IE TO PTD7 PULL-UP ENABLE IRQ2/ KEYBOARD INTERRUPT PTD0/KBD0 PTD7/KBD7 IRQ2 ACK2 DQ CK CLR V DD MODE2 SYNCHRO- NIZER IMASK2 PIN2... IRQ2DIS IRQ2/KEYBOARD INTERRUPT LATCH REQUEST Configurable Port Interrupts Block Diagram

External Interrupt Module MTT Keyboard Interrupt Pins Port D pins can be enable as port interrupts Interrupt requests are latched into the IRQ2/Keyboard Interrupt Latch Interrupt request is latched on falling edge Trigger may be edge sensitive only or level and edge sensitive Generate an IRQ2 interrupt request Vector address is $FFE0 and $FFE1 (68HC708XL36)

External Interrupt Module MTT Keyboard Interrupt Control Register (KBICR) Keyboard Interrupt Enable bits (KB7IE - KB0IE) –Enables corresponding keyboard interrupt pin to latch interrupt request –Port pin data direction automatically changed to input 1 = Corresponding Keyboard interrupt pin enabled and pull-up device on 0 = Corresponding Keyboard interrupt pin disabled and pull-up device off RESET: WRITE: READ: KBICR KB7IE KB6IE KB5IE KB4IE KB3IE KB2IE KB1IE KB0IE Keyboard Interrupt Control

External Interrupt Module MTT Summary RESET: WRITE: ACK2 ACK1 READ: 0 0 ISCR PIN2IMASK2MODE2IRQ2DISIMASK1MODE1 RESET: WRITE: READ: KBICR KB7IE KB6IE KB5IE KB4IE KB3IE KB2IE KB1IE KB0IE RESET:x11x1xxx WRITE: READ: CCR V 1 1HI N C Z