Latches and Flip-Flops Discussion D8.1 Section 13-9.

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Latches and Flip-Flops Discussion D8.1 Section 13-9

Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only on current input but also on past input values –Need some type of memory to remember the past input values

Cross-coupled Inverters State 1 State 2

~S-~R Latch ~S ~R Q ~Q ~S ~R Q ~Q X Y nand

~S-~R Latch ~S ~R Q ~Q ~S ~R Q ~Q X Y nand

~S-~R Latch ~S ~R Q ~Q X Y nand ~S ~R Q ~Q

~S-~R Latch X Y nand 1 0 Set ~S ~R Q ~Q ~S ~R Q ~Q

~S-~R Latch X Y nand 1 0 Set 1 0 Store ~S ~R Q ~Q ~S ~R Q ~Q

~S-~R Latch X Y nand 1 0 Set 1 0 Store ~S ~R Q ~Q ~S ~R Q ~Q

~S-~R Latch X Y nand 1 0 Set 1 0 Store ~S ~R Q ~Q ~S ~R Q ~Q

~S-~R Latch X Y nand 1 0 Set 1 0 Store 0 1 Reset ~S ~R Q ~Q ~S ~R Q ~Q

~S-~R Latch X Y nand 1 0 Set 1 0 Store 0 1 Reset ~S ~R Q ~Q ~S ~R Q ~Q

~S-~R Latch X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0 ~S ~R Q ~Q ~S ~R Q ~Q

~S-~R Latch X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0 To close or lock with or as if with a latch, To catch or fasten ~S ~R Q ~Q ~S ~R Q ~Q

S-R Latch ~S ~R Q ~Q S R CLK S R CLK ~S ~R Q ~Q Q 0 ~Q 0 Store Reset Set Disallowed X X Q 0 ~Q 0 Store

D Latch Q ~Q CLK D ~S ~R S R S R CLK Q ~Q Q 0 ~Q 0 Store Reset Set Disallowed X X 0 Q 0 ~Q 0 Store X 0 Q 0 ~Q 0 D CLK Q ~Q

D Latch Q ~Q CLK D ~S ~R S R X 0 Q 0 ~Q 0 D CLK Q ~Q Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

Recall the ~S-~R Latch ~S ~R Q ~Q ~S ~R Q ~Q X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 ~Q 0

Edge-triggered D Flip-flop

Edge-triggered D Flip-flop with asynchronous set and reset

D Flip-Flop X 0 Q 0 ~Q 0 D CLK Q ~Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

Each Xilinx macrocell contains a D flip-flop Controlled inverter

Each Xilinx macrocell contains a D flip-flop Note asynchronous preset x Note asynchronous reset y z

Divide-by-2 Counter CLK Q0 D = ~Q0 CLK DQ ~Q D = ~Q0 Q0 D ~Q0

module div2cnt ( Q,clr,clk ); input clr ; wire clr ; input clk ; wire clk ; output Q ; reg Q ; wire D ; assign D = ~Q; // D Flip-flop clk or posedge clr) if(clr == 1) Q = 0; else Q = D; endmodule div2cnt.abl CLK DQ !Q D = ~Q0 Q0 D ~Q0

J-K Flip-flops D = J & ~Q | ~K & Q J K D 0 0 Q ~Q

J-K Flip-flops

T Flip-flops D = T ^ Q TD 0Q 1 ~Q

T Flip-flops