20. Feb. 2002, LTP1 Electronics for the  e  experiment Short introduction and status Trigger electronics DAQ electronics Slow Control Developments useful for other experiments

20. Feb. 2002, LTP2 Search for  e  at MEG Detector LFV Process forbidden by SM oscillations expected to enhance LFV rate Present limit: (MEGA) SUSY Theories: ~ LFV Process forbidden by SM oscillations expected to enhance LFV rate Present limit: (MEGA) SUSY Theories: ~ Required:   stopping rate: 10 8 /s Resolutions (all FWHM):  E e : 0.7%  E  : 52.8 MeV  e  : 12 mrad  t e  : 150ps Required:   stopping rate: 10 8 /s Resolutions (all FWHM):  E e : 0.7%  E  : 52.8 MeV  e  : 12 mrad  t e  : 150ps E e = 52.8 MeV Kinematics  e  = 180° E  = 52.8 MeV e  

20. Feb. 2002, LTP3 Detector Design Tests & Design Assembly Engineering Run Data taking......

20. Feb. 2002, LTP4 Cryogenics Design

20. Feb. 2002, LTP5 Status update New xenon purification with SAES mono- torr getter filter. Should reduce all non- noble gases to < ppb level Very low noise on PMTs (1mV peak-to- peak)  0.2% resolution when summing all 240 PMTs PMT gain equalized reproducible with LED method to ~3%, limited by HV stability Beam time at TERAS starts today

20. Feb. 2002, LTP6 Trigger Requirements  Beam rate10 8 s -1  Fast LXe energy sum > 45MeV2  10 3 s -1   interaction point  e + hit point in timing counter  time correlation  – e s -1  angular corrlation  – e + 20 s -1  Beam rate10 8 s -1  Fast LXe energy sum > 45MeV2  10 3 s -1   interaction point  e + hit point in timing counter  time correlation  – e s -1  angular corrlation  – e + 20 s -1 E e = 52.8 MeV Kinematics  e  = 180° E  = 52.8 MeV e   M.C.

20. Feb. 2002, LTP7 LXe energy sum Total ~800 PMTs Common noise contributes significantly to analog sum AC coupling  Baseline drift How to evaluate  of shower center? Total ~800 PMTs Common noise contributes significantly to analog sum AC coupling  Baseline drift How to evaluate  of shower center?

20. Feb. 2002, LTP8 Digital Trigger Commodity electronics available –100 MHz FADC 10 bit (10$) –FPGA 100k Gates, 90kB, 230 MHz, 300 pins (100$) –SRAM 10ns, 128kB (30$) –LVDS 200Mb/s/line, (2$) –VME32/VME64 FADC FPGA FADC SRAM Trigger … PMT

20. Feb. 2002, LTP9 Latch Baseline Subtraction Baseline Subtraction Latch 10 bit 100 MHz Clock    - + <thr  + - Baseline Register Uses ~120 out of 5000 logic cells  8 channels/FPGA use 20% of chip Uses ~120 out of 5000 logic cells  8 channels/FPGA use 20% of chip Baseline subtracted signal LUT 10x10 Calibrated and linearized signal

20. Feb. 2002, LTP10 QT Algorithm original waveform smoothed and differentiated (Difference Of Samples) Threshold in DOS Region for pedestal evaluation integration area t Inspired by H1 Fast Track Trigger (A. Schnöning) Difference of Samples (= 1 st derivation) Hit region defined when DOS is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT  1ns resolution for 10ns sampling time Inspired by H1 Fast Track Trigger (A. Schnöning) Difference of Samples (= 1 st derivation) Hit region defined when DOS is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT  1ns resolution for 10ns sampling time

20. Feb. 2002, LTP11 Finding center of  shower  ε (|φ(center)-  (max. PMT)| 99%  Enough to find PMT with max. value

20. Feb. 2002, LTP12 Schema for max. finding 8 8 Latch B AA<B 8 Index bit 8 8 Latch B AA<B 8 Index bit Latch B AA>B 8 Index bit LSB MSB index value

20. Feb. 2002, LTP13 e + -  coincidence or e + counter LUT > 45MeV LUT AND  phi e + phi Trigger back-to back other veto LUT max PMT LXe Sum

20. Feb. 2002, LTP14 Trigger latency BS    Max T[ns] >45MeV   e+ AND 10 stages = 1024 chn... ADC......

20. Feb. 2002, LTP15 VME Boards VME Interface (Cypress) 3.3V 2.5V FADC LVDS FPGA SRAM FADC LVDS FPGA SRAM VME Interface (Cypress) 3.3V 2.5V LVDS FPGA SRAM LVDS FPGA SRAM LVDS Type1Type2 8 channels LVDS 8 channels clck, clear 48 bits output LVDS

20. Feb. 2002, LTP16 Board hierarchy 42 Type 1 boards for 600 channels 6 Type 2 boards (VME 9U) 3 VME crates (2x6U, 2x9U) Total latency 350ns Processing power 600 * 100 MHz * 10 bit = 75 GB/s “Golden Rule”: plan for FPGAs with 2x gates Totally re-programmable Estimated costs: 230k$ Made by INFN, Pisa 42 Type 1 boards for 600 channels 6 Type 2 boards (VME 9U) 3 VME crates (2x6U, 2x9U) Total latency 350ns Processing power 600 * 100 MHz * 10 bit = 75 GB/s “Golden Rule”: plan for FPGAs with 2x gates Totally re-programmable Estimated costs: 230k$ Made by INFN, Pisa

20. Feb. 2002, LTP17 Prototype board ADC Signal- Generator DAC FPGA Peter Dick

20. Feb. 2002, LTP18 DAQ Hardware Requirements n E[MeV] ee Michel edge t PMT sum e    e    e  51.5 MeV MeV  ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) Timely separated  ’s need waveform digitizing > 300 MHz If waveform digitizing gives timing <100ps, no TDCs are needed  ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) Timely separated  ’s need waveform digitizing > 300 MHz If waveform digitizing gives timing <100ps, no TDCs are needed ~100ns

20. Feb. 2002, LTP19 Fast waveform Digitizing VME Interface (Cypress) 3.3V 2.5V FADC LVDS FPGA SRAM FADC LVDS FPGA SRAM 8 channels LVDS 8 channels clck, clear 48 bits output Trigger boards can directly be used for Drift Chamber (10ns sampling  1ns interpolation  2-3ns chamber resolution) Waveforms stored in SRAM, sparcified readout via LVDS Calorimeter readout needs sampling with > 1GHz Analog Waveform Domino Sampling Chip 2GHz40MHz, 12 bit DSCFADC FPGA SRAM

20. Feb. 2002, LTP20  Domino Sampling Chip 0.5 – 1.2 GHz sampling speed 128 sampling cells Readout at 5 MHz, 12 bit ~ 100 CHF/channel Needed: 2.5 GHz sampling speed Circular domino wave 1024 sampling cells 40 MHz readout < 100ps accuracy

20. Feb. 2002, LTP21 Domino Ring Sampler (DRS) Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin) Readout 40 MHz 12 bit 1024 bins  150ns waveform + 350ns delay Free running domino wave, stopped with trigger Sampling speed 2 GHz (500ps/bin) Readout 40 MHz 12 bit 1024 bins  150ns waveform + 350ns delay input

20. Feb. 2002, LTP22 Domino Cell domino enable “Tail-biting” mechanism to chop off domino wave Coupling in of Domino Start in all cells for homogeneity Minimal number of components in critical path Global Domino Enable Capacitor to slow down speed “Tail-biting” mechanism to chop off domino wave Coupling in of Domino Start in all cells for homogeneity Minimal number of components in critical path Global Domino Enable Capacitor to slow down speed

20. Feb. 2002, LTP23 Domino Wave stability NMOS=PMOS NMOS<PMOS w/o tail biting NMOS<PMOS with tail-biting “starving”widenedstable

20. Feb. 2002, LTP24 Gate sampling signal trigger gate 500ps50ps Domino stop only accurate by one cell (500ps) Need 50ps timing resolution Domino stop only accurate by one cell (500ps) Need 50ps timing resolution Trigger gate sampling

20. Feb. 2002, LTP25 DAQ Board 8 inputs trigger gate FADC 3 state switches FPGA SRAM shift register 9 channels  1024 bins / 40 MHz = 230 ms  acceptable dead time Zero suppression in FPGA QT Algorithm in FPGA (store waveform if multi-hit) Readout controller in FPGA (instead pattern generator) 9 channels  1024 bins / 40 MHz = 230 ms  acceptable dead time Zero suppression in FPGA QT Algorithm in FPGA (store waveform if multi-hit) Readout controller in FPGA (instead pattern generator) 40 MHz 12 bit VME Interface (Cypress) 3.3V 2.5V 8 channel DRS Trigger Input Board inter-connect FPGA SRAM FADC 8 channel DRS 8 channel DRS FADC 8 channel DRS Trigger BUS (2 nd level tr.)

20. Feb. 2002, LTP26 Status DRS Simulation finished in AMS 0.35  process Layout started Switch to 0.25  process First version summer ’02 Readout with trigger prototype board Costs per channel: ~25$ (board) + 6$ (chip)

20. Feb. 2002, LTP27 DAQ Muegamma PMT FADC FPGA trigger 2GHz 40MHz DC Trigger Board trigger 100MHz DSC Trigger Board CPU LXe e + wires strips Waveform or QT readout DAQ board Waveform or QT readout Split and Preamplifier optional 2 nd level trigger

20. Feb. 2002, LTP28 “Redefinition” of DAQ Conventional New AC couplingBaseline subtraction Const. Fract. Discriminator DOS – Zero crossing ADCNumerial Integration TDC Bin interpolation (LUT) Wafeform Fitting Scaler (250 MHz)Scaler (50 MHz) OscilloscopeWaveform sampling 400 US$ / channel50 US$ / channel TDC Disc. ADC Scaler Scope FADC FPGA SRAM DSC ~GHz 100 MHz

20. Feb. 2002, LTP29 Applications in other experiments Technology in house (pool) Substitution of old electronics (ADC, Scaler, Discriminators) LVDS-NIM converter and VME necessary Integration in new experiments VME Interface (Cypress) 3.3V 2.5V FADC LVDS FPGA SRAM FADC LVDS FPGA SRAM LVDS PMT Beam Counters calorimeter  t trigger = 10ns  t TDC  1ns

20. Feb. 2002, LTP30 Slow Control HV PC RS Temperature, pressure, … GPIB Valves ??? 15° C heater PLC 12: : : : : : : : MIDAS DAQ Ethernet Terminal Server

20. Feb. 2002, LTP31 Slow Control Bus HV Temperature, pressure, …Valves heater MIDAS DAQ

20. Feb. 2002, LTP32 LXe calorimeter HV requirements 12 stage 1000V  g = (  U) 12  1V accuracy = 1.2% gain variation Need <0.3V accuracy over full temperature range Low ripple 1000 channels ~ 200k$ commercially Fast readout for monitoring (RS232 would take ~3 min to read) 12 stage 1000V  g = (  U) 12  1V accuracy = 1.2% gain variation Need <0.3V accuracy over full temperature range Low ripple 1000 channels ~ 200k$ commercially Fast readout for monitoring (RS232 would take ~3 min to read)

20. Feb. 2002, LTP33 Field Bus Solutions CAN, Profibus, LON available Node with ADC ~100$ Interoperatibility not guaranteed Protocol overhead Local CPU? User programmable? How to integrate in HV (CAEN use CAENET) CAN, Profibus, LON available Node with ADC ~100$ Interoperatibility not guaranteed Protocol overhead Local CPU? User programmable? How to integrate in HV (CAEN use CAENET) Reinhard Schmidt

20. Feb. 2002, LTP34 RS485 bus Similar to RS-232 but –Up to 256 (1/8 load) units can be connected to a single segment –single line, half duplex –differential twisted pair –Segment length up to km MAX 1483 transceiver chip for HV control MAX 1480 for opto decoupled applications Use repeater to extend to many segments

20. Feb. 2002, LTP35 Generic Node ADuC812 / C8051F000 Microcontrollers MAX 1483 Tranceiver Flat ribbon connector Power through bus Costs ~30$ Piggy back board ADuC812 / C8051F000 Microcontrollers MAX 1483 Tranceiver Flat ribbon connector Power through bus Costs ~30$ Piggy back board

20. Feb. 2002, LTP36 2 versions Generic node with signal conditioning (OP- AMPs) Sub-master with power supply and PC connection (Parallel Port, USB planned) Integration on sensors, in crates RS232 node planned BUS Oriented Crate Oriented 19” crate with custom backplane Generic node as piggy-back Cards for analog IO / digital IO / temperature / 220V / … Crate connects to parallel port (USB planned)

20. Feb. 2002, LTP37 Protocol Asynchronous 345 kBaud 16-bit addressing (65536 nodes) CRC-code for error detection Optional acknowledge Concept of channels and configuration parameters (256 each per node) Asynchronous 345 kBaud 16-bit addressing (65536 nodes) CRC-code for error detection Optional acknowledge Concept of channels and configuration parameters (256 each per node) commandLSBMSBCRC address command commandchannelvalueCRC write data node param1 param2 param3 channel1 channel2 channel3 ADC port 1 Byte

20. Feb. 2002, LTP38 Midas Slow Control Bus 256 nodes, with one level of repeaters Bus length ~500m opto-isolated Boards for voltage, current, thermo couples, voltage output, TTL IO, 220V output, available from pool on request Readout speed: 0.3s for 1000 channels C library, command-line utility, Midas driver, LabView driver Connects to parallel port, USB planned Nodes are “self-documenting” Configuration parameters in EEPROM on node Node CPU can operate autonomously for interlock and regulation (PID) tasks (C programmable) Nodes can be reprogrammed over network nodes, with one level of repeaters Bus length ~500m opto-isolated Boards for voltage, current, thermo couples, voltage output, TTL IO, 220V output, available from pool on request Readout speed: 0.3s for 1000 channels C library, command-line utility, Midas driver, LabView driver Connects to parallel port, USB planned Nodes are “self-documenting” Configuration parameters in EEPROM on node Node CPU can operate autonomously for interlock and regulation (PID) tasks (C programmable) Nodes can be reprogrammed over network

20. Feb. 2002, LTP39 LabView Logger Used for POLDI detector HV and gas monitoring Graph, logging and alarm notification

20. Feb. 2002, LTP40 High Voltage System

20. Feb. 2002, LTP41 HV performance Regulates common HV source V, ~1mA DAC 16bit, ADC 14bit Current trip ~10  s Self-calibration with two high accuracy reference voltages Accuracy <0.3V absolute Boards with 12 channels, crates with 192 channels 30$/channel Regulates common HV source V, ~1mA DAC 16bit, ADC 14bit Current trip ~10  s Self-calibration with two high accuracy reference voltages Accuracy <0.3V absolute Boards with 12 channels, crates with 192 channels 30$/channel Prototype

20. Feb. 2002, LTP42 Conclusions Lots of new electronics for Muegamma Can be useful for other experiments Knowledge and support in-house Open to suggestions and modifications Lots of new electronics for Muegamma Can be useful for other experiments Knowledge and support in-house Open to suggestions and modifications Credits to Reinhard Schmidt and Peter Dick

20. Feb. 2002, LTP43 Muegamma Web Site Transparencies: Cake: