Lecture 6 CES 522 Latches and Flip-Flops Jack Ou, Ph.D.

Sequential Circuits New output are dependent on the inputs and the preceding values of outputs. Characteristic: output nodes are intentionally connected back to inputs. Basic sequential circuits: – Level Sensitive Circuits – Edge Sensitive Circuits

Small Perturbation to a Basic Inverter

Large Perturbation to a Basic Inverter

Application: SRAM

Metastable Point

Small Perturbation from the Metastable Point

Intel’s Random Bit Generator

Latches Latches are level sensitive. Latches propagate values from input to output continuously. S sets Q =1; R sets Q=1 – Active low inputs are enabled by 0s. – Active high inputs are enabled by 1s.

SR Latch with NOR Gates t PDSQ =2 NOR gate delays. t PDRQ_ =1 NOR gate delay Forbidden State SR are trigger pulses which can return to zero once Q is set. Active High inputs

SR Latch with NAND Gates Active low inputs

D Latch

D-latch Operation

D-Latch (CK=0) 0 D DB 0 0

D-Latch (CK=1) 1 D DB D D

Analyze D Latch Using Boolean Algebra

Transistor Level Implementation of D-Latch

D-Latch (CLK=1,D=1) VDD 0

Standard Library D Latch CLK=VDD (Q=D)

Standard Library D Latch CLK=0V (Hold State)

JK Flip-Flop

JK Flip Flop (CK=0) 0 1 1

JK Flip Flop (CK=1,J=K=0)

JK Flip Flop (CK=1,J=K=1) If CK is on for a long time, the output of this JK flip flip will toggle! The pulse width of CK must be less than the propagation delay time through the loop.

JK Flip Flop (CK=1,J=0→1,K=0)

CK=1, J=0 → 1, K=0 Regardless of initial value of Q, – CK=1, J= → 1, K=0 will set the updated value of Q to a 1.

JK Flip Flop (CK=1,J=0,K= 0→ 1)

1 1→0 →

CK=1, J=0, K=0 → 1 Regardless of initial value of Q, – CK=1, J= 0, K=0 → 1 will set the updated value of Q to a 0.

JK Flip-Flop J=1, K=1 can lead to oscillation if the width of CK is longer than propagation delay.

JK Master-Slave Flip-Flop The slave latch is insulated from changes of J and K when CK=1 Q holds its current value. The Q of the master latch is updated when CK=1.

JK Master-Slave Flip-Flop (CK=1) JK 00

JK

JK

JK

JK

JK If J catches a glitch, it is stuck the master latch! 1 0

Edge Sensitive Circuits

JK Negative Edge-Triggered Flip-Flop 1 Active-Low Devices 1 1 Disabled “hold” mode

JK Negative Edge-Triggered Flip-Flop Active-Low Devices 1 1 “hold” mode enabled

JK Negative Edge-Triggered Flip-Flop 1 1 “hold” mode enabled →disabled

JK Negative Edge-Triggered Flip-Flop CK The NAND latch is only updated for a short interval immediately after the negative edge, before being set to the hold.

Update JnJn KnKn Q n

J=0; K=1 JnJn KnKn Q n

J=1; K=0 JnJn KnKn Q n+1 10Q11 01Q n =0 S= Q n =1 S=1 1Q n =1 Q n+1 =1

Negative Edge Triggered Flip-FLop JnJn KnKn Q n Q11

D Flip-Flop

D-Flop 1 2 CK of latch 2 CK of latch 1 X OUT=X X=IN 1: Hold 2: Track 2:hold 1:track OUT samples IN at the positive edge of the clock

Timing Diagram

Definition Setup time: the time that the incoming data must be stable before the clock arrives Hold time: the length of time that the data remains stable after the clock arrives for proper operation If the data is stable before the setup time and continues to be stable after the hold time, the flop will work properly. If the data arrives within the period designated by the setup and hold times, the flop may or may not capture the correct value.

CLK-Q The delay from the time that the clock arrives to the point that the output stabilizes. In reality the data must arrive at the setup time before the clock hits and the output is valid after the CLK-Q delay.