The World Leader in High Performance Signal Processing Solutions Qualification of the Transfer of the BIPOLAR SV process from ADWIL ADLK 8”

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Presentation transcript:

The World Leader in High Performance Signal Processing Solutions Qualification of the Transfer of the BIPOLAR SV process from ADWIL ADLK 8”

 Qualification of the BIPOLAR SV process in ADLK will include Device Level Testing and Product Level Testing.  Parts to be transferred are: OP297 OP497 Overview of Qualification

OP297 Product Level Qualification Plan  Qualification will be performed per Analog Devices specification ADI ADI0012 is the procedure for qualification for New or Revised Processes or Products. The Qualification Report will be available after completion, upon request. Sample size typically 77/lot 1 Preconditioned Per JEDEC/IPC J-STD-020 OP297 Qualification T EST Standard C ONDITIONS Quantities High Temperature Operating Life 1 JEDEC 125C biased1x77 Early Life FailureJEDEC biased1x667 Highly Accelerated Stress Test (HAST) 1 JEDEC 85%RH 131C biased3x77 Temperature Cycle 1 JEDEC JESD22-A104500cycles -65C/+150C1x77 Autoclave 1 JEDEC 100%RH 121C unbiased1x77 High Temperature Storage JEDEC 150CSubstitute Data Latch-UpJEDEC Standard 78+25C Biased single duration 100/99mA1x6 Electrostatic Discharge Human Body Model ESD Association STM Std Sample 1 Zap per polarity p/f 1000V/999V1x24* Electrostatic Discharge Field-Induced Charged Device Model ESD Association STM All pins 3 zaps per polarity p/f 500V/499V1x18* *ESD HBM & FICDM will meet existing product process requirements

OP497 Product Level Qualification Plan  Qualification will be performed per Analog Devices specification ADI ADI0012 is the procedure for qualification for New or Revised Processes or Products. The Qualification Report will be available after completion, upon request. Sample size typically 77/lot 1 Preconditioned Per JEDEC/IPC J-STD-020 OP497 Qualification T EST Standard C ONDITIONS Quantities High Temperature Operating Life 1 JEDEC 125C biasedSubstitute Data Early Life FailureJEDEC biasedSubstitute Data Highly Accelerated Stress Test (HAST) 1 JEDEC 85%RH 131C biasedSubstitute Data Temperature Cycle 1 JEDEC JESD22-A104500cycles -65C/+150CSubstitute Data Autoclave 1 JEDEC 100%RH 121C unbiasedSubstitute Data High Temperature Storage JEDEC 150CSubstitute Data Latch-UpJEDEC Standard 78+25C Biased single duration 100/99mA1x6 Electrostatic Discharge Human Body Model ESD Association STM Std Sample 1 Zap per polarity p/f 1000V/999V1x24* Electrostatic Discharge Field-Induced Charged Device Model ESD Association STM All pins 3 zaps per polarity p/f 500V/499V1x18* *ESD HBM & FICDM will meet existing product process requirements