INTRODUCTION TO SEQUENCIAL CIRCUIT

Introduction Combinational circuits: Sequential circuits: contain no memory elements the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends on present inputs and present states (pre. inputs) (inputs, current state) Þ (outputs, next state) Combinational logic refers to circuits whose output is strictly dependent on the present value of the inputs. Once the input values are changed, the information regarding the pre- vious inputs is lost; in other words, combinational logic circuits have no memory. In many applications, information regarding input values at a certain instant of time is needed at some future time. Circuits whose output depends not only on the present values of the input but also on the past values of the inputs are known as sequential logic circuits. The mathematical model of a sequential circuit is usually referred to as a sequential machine or a finite state machine.

General model of a sequential logic circuit. Sequential Circuits A general model of a sequential circuit is shown in Figure 4.1. As can be seen in the diagram, sequential circuits are basically combinational circuits with the additional property of memory (to remember past inputs). The combinational part of the circuit receives two sets of input signals: primary (coming from the circuit environment) and secondary (coming from the memory). The particular combination of secondary input variables at a given time is called the present state of the circuit; the secondary input variables are also known as state variables. If there are m secondary input variables in a sequential circuit, then the circuit can be in anyone of 2mdifferent present states. The outputs of the combinational part of the circuit are divided into two sets. The primary outputs are available to control operations in the circuit environment, whereas the secondary outputs are used to specify the next state to be assumed by the memory. The number of secondary output variables, often called the excitation variables, depends on the type of memory element used. General model of a sequential logic circuit.

Sequential Circuits A sequential circuit is specified by a time sequence of inputs, outputs and internal states Sequential circuits must be able to remember the past history Flip-flops: most commonly used memory devices A function of - present inputs & - present state of memory elements (the past sequence of inputs)

Sequential Circuit--- Why? comparator input output Add more memory elements! Iteration 1: A=0110 B=1100 Iteration 2: if (A<B) C=1100 D=0111 else C=0011 D=1000 4-bit Comparator

Synchronous clocked sequential circuit Use clock pulses generated by a clock generator 1 1 2 2 2 Synchronous clocked sequential circuit

Types of Sequential Circuits depending on the timing of their signals Synchronous sequential circuits Storage elements are affected at discrete time instants Use clock pulses in the inputs of storage elements Asynchronous sequential circuits Storage elements are affected at any time instant

Synchronous Sequential Circuits Storage elements are affected only with the arrival of each pulse The storage elements used in the clocked sequential circuits are called “flip-flops” Synchronous Use clock pulses in the inputs of storage elements

Synchronous Sequential Circuits a master-clock generator to generate a periodic train of clock pulses the clock pulses are distributed throughout the system clocked sequential circuits (most popular) no instability problems the memory elements: flip-flops binary cells capable of storing one bit of information two outputs: one for the normal value and one for the complement value maintain a binary state indefinitely until directed by an input signal to switch states

Latches and Flip-Flops 8/22/2012 – ECE 3561 Lect 2 What is the difference? Flip-flops use a clock and are clock edge triggered When the clock edge occurs the data on the data inputs determines the next state of the flip-flop Latches are level sensitive Latches are very common in VLSI circuits Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU The basis 8/22/2012 – ECE 3561 Lect 2 How do you design logic that holds state? Logic gates are feed forward devices who’s output depends on the value of the inputs So how to create a device that holds a state? Feedback!! Copyright 2012 - Joanne DeGroat, ECE, OSU

Latch vs. Flip-Flop Latch positive-edge triggered CLK Q D CLK negative-edge triggered CLK CLK

Latches The most basic types of flip-flops operate with signal levels latch All FFs are constructed from the latches introduced here A FF can maintain a binary state indefinitely until directed by an input signal to switch states Two NOR gates Set=1Q=1, Reset=1Q=0

Latches IF R=0 S=0 1 1 1 1 1 1 IF R=1 S=0 1 1 1 1 1 Step 1: red number Step 2: yellow number Step 3: green number Step 4: black number 1 1 1 1 1 1

Latches IF 1 1 1 R=1 1 S=1 1  Q=0 Q’= 0 After that, R=0 and S=0 1 1 1 Step 1: red number Step 2: yellow number Step 3: green number Step 4: black number 1  Q=0 Q’= 0 After that, R=0 and S=0 Wrong! 1 1 1 1 1 …

Latches SR latch (S,R)= (0,0): no operation S R Q’ Q 0 0 * * // a stable state in the previous state 1 0 0 1 // change to another stable state “Set” 0 0 0 1 // remain in the previous state 0 1 1 0 // change to another stable state “Reset” 0 0 1 0 // remain in the previous state 1 1 0 0 // oscillate (unpredictable) if next SR=00 SR latch (S,R)= (0,0): no operation (S,R)=(0,1): reset (Q=0, the clear state) (S,R)=(1,0): set (Q=1, the set state) (S,R)=(1,1): indeterminate state (Q=Q'=0) Under normal condition, (S,R) = (0,0) Set (S,R)=(1,0) can store a 1 in it. Then the output maintains 1 even the input is set as (S,R)=(0,0) the condition should be avoided Q  a memory/storage unit to store a bit (by setting different R and S)

SR Latch with NAND gates (S’R’ latch) reset set SR latch with NAND gates (c) Graphic symbol S’R’ latch

SR Latch with Control Input The complement output of the previous R’S’ latch. S_ R_ 1/S' 1/R' 0/1 En=0, no change En=1, enable

The Set-Reset (SR) Latch 8/22/2012 – ECE 3561 Lect 2 The circuit has no memory Output depends not only on present inputs but the state of the latch when the current inputs were applied. The state 1 1 on the inputs not allowed. Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU HDL code for SR Latch 8/22/2012 – ECE 3561 Lect 2 The core of the model --set up dataflow for SR latch Q <= R NOR Qbar AFTER 5 ns; Qbar <= S NOR Q AFTER 5 ns; Apply stimulus to S and R What does simulation show Copyright 2012 - Joanne DeGroat, ECE, OSU

HDL simulation of SR latch 8/22/2012 – ECE 3561 Lect 2 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU The next state 8/22/2012 – ECE 3561 Lect 2 The state 11 is not allowed S=1 Q to 1 R=1 Q to 0 S and R 00 Hold state Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU Next state truth table 8/22/2012 – ECE 3561 Lect 2 From the table you can get the next state equation Here – Q+ = S + R’Q An equation that expresses the state of a latch (or flip flop) in terms of its present state and inputs is referred to as the characteristic equation. Copyright 2012 - Joanne DeGroat, ECE, OSU

level triggered (level-sensitive) D Latch (Transparent Latch) S_ 1/D' 0/1 R_ 1/D eliminate the undesirable conditions of the indeterminate state in the RS flip-flop D: data D Þ Q when En=1; no change when En=0 Q D En level triggered (level-sensitive) When En=1, Q changes as soon as D changes

Copyright 2012 - Joanne DeGroat, ECE, OSU The D Latch 8/22/2012 – ECE 3561 Lect 2 The D Latch is the most common element in CMOS design. Copyright 2012 - Joanne DeGroat, ECE, OSU

Timing diagram for a D Latch 8/22/2012 – ECE 3561 Lect 2 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU The D F/F The D Flip-Flop has edge triggered operation Can be positive edge triggered (as here) or negative edge triggered 8/22/2012 – ECE 3561 Lect 2 Copyright 2012 - Joanne DeGroat, ECE, OSU

Timing for a D Flip-Flop 8/22/2012 – ECE 3561 Lect 2 Important to note relationships Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU D F/F Behavior Some important timing parameters Clock to output Setup and hold time 8/22/2012 – ECE 3561 Lect 2 Copyright 2012 - Joanne DeGroat, ECE, OSU

D F/F with Preset and Clear Can add preset and clear for easier circuit initialization. 8/22/2012 – ECE 3561 Lect 2 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU Scan Chains D F/F are the F/F used in scan chains. What are scan chains? 8/22/2012 – ECE 3561 Lect 2 Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU Scan Chains 8/22/2012 – ECE 3561 Lect 2 Can use scan chains to inputs data or extract data Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU The T Flip Flop Toggle Flip Flop 8/22/2012 – ECE 3561 Lect 2 Copyright 2012 - Joanne DeGroat, ECE, OSU

More on Basic Sequential Elements 8/22/2012 – ECE 3561 Lect 2 The S-R F/F Q*=S+R’Q The Toggle F/F Q*=Q’ Q* is next value or next state Copyright 2012 - Joanne DeGroat, ECE, OSU

Copyright 2012 - Joanne DeGroat, ECE, OSU D F/F and J/K F/F 8/22/2012 – ECE 3561 Lect 2 D F/F Q* = D J/K F/F Q*=JQ’+K’Q Copyright 2012 - Joanne DeGroat, ECE, OSU

Flip-Flops A trigger The state of a latch or flip-flop is switched by a change of the control input Level triggered – latches Edge triggered – flip-flops Level triggered Edge triggered Edge triggered

Problem of Latch If level-triggered flip-flops are used the feedback path may cause instability problem (since the time interval of logic-1 is too long) multiple transitions might happen during logic-1 level Edge-triggered flip-flops the state transition happens only at the edge eliminate the multiple-transition problem

Edge-Triggered D Flip-Flop Two designs to solve the problem of latch: Master-slave D flip-flop Edge-trigger D flip-Flop Master-slave D flip-flop two separate latches a master latch (positive-level triggered) a slave latch (negative-level triggered) o

Master-slave D flip-flop Two D latches and one inverter The circuit samples D input and changes its output Q only at the negative-edge of CLK isolate the output of FF from being affected while its input is changing new value old value CLK=1, enabled CLK=0, disabled CLK=1, disabled CLK=0, enabled Old value is equal to the new value only at the instant of CLK’s falling edge positive-edge

Master-slave D flip-flop CP = 1: (S,R) Þ (Y,Y'); (Q,Q') holds CP = 0: (Y,Y') holds; (Y,Y') Þ (Q,Q') (S,R) could not affect (Q,Q') directly the state changes coincide with the negative-edge transition of CP

Edge-Triggered Flip-Flops the state changes during a clock-pulse transition SR latch with NAND gate A D-type positive-edge-triggered flip-flop three SR latches

Edge-Triggered Flip-Flops (S,R) = (0,1): Q = 1 (S,R) = (1,0): Q = 0 (S,R) = (1,1): no operation (S,R) = (0,0): should be avoided If Clk=0  S=1 and R=1  no operation. Output Q remains in the present state. 1 1 2 3 4 1 1 1 1 1 1 10 1 1 If Clk=1 and D=0 R=0  Reset. Output Q is 0. Then, if D changes to 1, R remains at 0 and Q is 0. 1 1

Edge-Triggered Flip-Flops (S,R) = (0,1): Q = 1 (S,R) = (1,0): Q = 0 (S,R) = (1,1): no operation (S,R) = (0,0): should be avoided If Clk=0 S=1 and R=1  no operation. Output Q remains in the present state. 1 2 3 4 1 1 If Clk=1 and D=0 R=0  Reset. Output Q is 0. Then, if D changes to 1, R remains at 0 and Q is 0. 1 0(new) 1(old) 1 1 Then, Clk=0  S=1, R=1  no operation (Q=0) Then, if Clk=1 and D=1 S=0 Set. Output Q is 1. (see the blue dot-line flow) Then, if D changes to 0, S remains at 0 and Q=1; 1 1

Positive-Edge-Triggered Flip-Flops Summary Clk=0: (S,R) = (1,1), no state change Clk=: state change once Clk=1: state holds eliminate the feedback problems in sequential circuits All flip-flops must make their transition at the same time