Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: basic construction principles

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET The abstraction level of our study: SYSTEM MODULE + GATE CIRCUIT DEVICE n+ SD G V out V in

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Recall: CMOS gates ► nMOS network: pulls down the output to GND: Pull-Down Network (PDN) ► pMOS network: pulls up the output to VDD: Pull-Up Network (PUN) ► PUN and PDN are dual networks (duality both in terms of graph topology and elements) F(In 1,In 2,…In N ) V DD In 1 In 2 In N In 1 In 2 In N PUN PDN … … Y A B VDD A Y B

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Complex gate – still "simple": C AB X = !((A+B)(C+D)) B A D V DD X X GND AB C PUN PDN C D D A B C D

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Creating dual networks CA E DB CA E DB

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Dynamic MOS logic ► Principle: 2 phase operation  a switching pMOS transistor charges a capacitor to the VDD voltage: pre-charge phase  in the next phase the capacitor is disconnected from VDD and it is discharged or is left intact through an nMOS logic circuit (according to the logic function realized by this PDN): this is the evaluation phase In 1 In 2 PDN In 3 MeMe MpMp Φ Φ Out CLCL Φ t pre-charge evaluation

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Dynamic gates In 1 In 2 PDN In 3 MeMe MpMp Φ Φ Out CLCL Φ Φ A B C MpMp MeMe Two phase operation: Precharge (Φ = 0) Evaluate (Φ = 1)

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Dynamic gates In 1 In 2 PDN In 3 MeMe MpMp Φ Φ Out CLCL Φ Φ A B C MpMp MeMe on off 1 on !((A&B)|C) If the output of a dynamic gate is discharged, it can not be discharged again until charged up in a pre-charge phase Two phase operation: Precharge (Φ = 0) Evaluate (Φ = 1)

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Major properties of dynamic gates ► The logic function is realized by the PDN  instead of 2N transistors only N+2 transistors are needed  smaller area than in in case of static CMOS ► Geometrical ratios do not play important role in the operation ► There is only dynamic power consumption ► A pre-charge clock signal is needed

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Dynamic operation CLK In 1 In 2 In 3 In 4 Out In & CLK Out Time, ns Voltage Evaluate Precharge

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Application of transmission gates ► The full adder realized by conventional static CMOS technique is too complex, requires too many transistors. ► Simplification: application of transmission gates ► Logic function is created not only by switching in the VDD-GND conduction path  switch inserted anywhere in a signal path  analog switch in a digital circuit

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Logic with transmission gates ► In CMOS: n/p transistors with inverted control (gate) voltages ► less transistors are needed ► reversible signal path ► no static power consumption ► limitation: insertion resistance – do not use more than 4 transmission gates in a signal path Transmission gate with inverted control Transmission gate with built- in inverter

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Static CMOS full adder B BB BB B B B A A A A A A A A C in !C out !Sum !C out = !C in & (!A | !B) | (!A & !B) C out = C in & (A | B) | (A & B) !Sum = C out & (!A | !B | !C in ) | (!A & !B & !C in ) Sum = !C out & (A | B | C in ) | (A & B & C in )

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Examples with transmission gates ► Typical: XOR, mux/demux  XOR gate:  4 input MUX: A B Y = A XOR B D0 D1 D2 D3 S0 NS0 Y NS1 S0 S1 S0S1NS0NS1 Y D3 D1 D2 D0

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Layout of a TG MUX GND V DD In 1 In 2 SS SS S S S In 1 F F F = !(In 1  S + In 2  S)

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Full adders with TG-s Sum C out A B C in 16 tr.

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Static CMOS full adder B BB BB B B B A A A A A A A A C in !C out !Sum !C out = !C in & (!A | !B) | (!A & !B) C out = C in & (A | B) | (A & B) !Sum = C out & (!A | !B | !C in ) | (!A & !B & !C in ) Sum = !C out & (A | B | C in ) | (A & B & C in ) 24 tr.

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Storage circuits: dynamic D ff ► Dynamic latch & ff  "Analog SH" circuits in a digital environment  Storage capacitor: input capacitance of the inverter  Two latches in series, controlled by non-overlapping signals: master-slave FF C IN EN D/Q DQ CK 2 CK 1 CK 2 CK 1

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Storage circuits: dynamic D ff ► Simplified version:  No need for a second, non-overlapping CLK  transmission gate with inverted control DQ CLK /CLKCLK

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Static latches and ff-s ► Can be constructed from logic gates with feedback loops Q /Q /R /S EN D Q /Q RS-latch D-latch 5 cells, 18 transistors Extended: D-latch

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET D latch ► with OR-AND-INVERT gate: The dynamic version took less space/transistors Q /END/D /Q D /EN Q /Q

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET D flip-flop ► two D latches in series with inverted clock signal QDQD QN D CLK Q /Q

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Memories – hierarchy Second Level Cache (SRAM) Control Datapath Secondary Memory (Disk) On-Chip Components RegFile Main Memory (DRAM) Data Cache Instr Cache ITLB DTLB eDRAM Speed (ns):.1’s 1’s 10’s 100’s 1,000’s Size (bytes): 100’s K’s 10K’s M’s T’s Cost: highest lowest

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Semiconductor memories RWMNVRWMROM Random Access Non-Random Access EPROMMask- programmed SRAM (cache, register file) FIFO/LIFOE 2 PROM DRAMShift Register CAM FLASHElectrically- programmed (PROM) See the structures later

Budapest University of Technology and Economics Department of Electron Devices MOS circuits © András Poppe, BME-EET Development of DRAMs See the structures later