Altera FLEX 10K technology in Real Time Application

Real Time Prototyping Method A key possibility to accelerate the performance of FPGA designs is the utilization of the architectural features of modern FPGAs. The way to do this is to process one by one the critical blocks of the design and to decide about the implementation strategy for each block. As an example, a case study of a microprocessor circuit is presented. The microprocessor should be able to work in real time at 10 MHz frequency. To reach this speed in the Altera FLEX 10KA technology, a special implementation strategy was elaborated for the microprocessor’s RAM and ALU blocks.

Contd… The recent FPGAs exceed 100K gates capacities and 100 MHz speeds. The latest architectures incorporate embedded memories, enhancements of logic blocks, sophisticated interconnect topologies and hierarchical structuring. Altera FLEX 10K family contains up to 100K gates and 24,576 bits of embedded memory; the FLEX 10KA family contains up to 250,000 gates. The FLEX 10K embedded array can be used to provide on-chip memory in the form of asynchronous or synchronous RAM, ROM and FIFO functions and can support 80 MHz cycle time. Utilization of embedded FPGA resources is a key for obtaining a prototype working at high speeds. But it often requires a detailed analysis of the design and individual processing of the critical blocks.

Prototyping Flow There exist two prototyping flows to produce an FPGA implementation for an ASIC design: => synthesize in parallel the ASIC and the FPGA net lists starting from the HDL description; =>synthesize first an ASIC netlist from the HDL netlist and then migrate the ASIC netlist to FPGA netlist by a technology migration tool. The second flow provides the closer correspondence between the ASIC and the FPGA netlists but it requires often manual description of ASIC libraries, and in addition, some sub-micron gates are difficult to describe.

Flow Diagram

Case Study : microprocessor The case study example is a 16-bit microprocessor which will be implemented in the Altera FLEX 10K technology. The design is described in VHDL language. The architecture and the instruction set of the microprocessor are optimized for high-performance peripheral controllers. It contains an instruction latch and decoder, state machine, status register, priority encoder, 32-word by 16-bit RAM, barrel shifter, ALU, data latch, three-state output buffers and accumulator. The microprocessor may execute byte and word instructions. The design is described in VHDL language.

Contd… ALU: – The microprocessor contains a 16-bit ALU with adder to perform arithmetical operations. The ALU is capable of operating on either one, two or three operands, depending upon the instruction being executed. 32*16 Bit RAM: – The 32-word by 16-bit RAM should be able to work in8-bit and 16-bit mode. For byte instructions, only the lower eight bits are written into. For word instructions, all 16-bits are written into. – When implemented on FLEX10K device as ”glue”, the propagation delay of this RAM is 43.8ns.

Contd… Barrel Shifter and Decoder  The 16-bit barrel shifter is used as one of the ALU inputs and permits data rotating from either the accumulator or the data latch.  The propagation time of the area optimized macro block lpm clshift is more than one produced by the ”glue” mapping. The glue implementation is maintained in the final version.  The microprocessor decoder performs the instruction decoding and sends the control signals to all the microprocessor blocks.  The decoder structure is specific for the given microprocessor circuit and no existing block may replace it. The only solution is to implement the decoder block by the glue strategy

Experimental results

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