Microprocessors General Features To be Examined For Each Chip Jan 24 th, 2002

Memory Structure Addressable units Addressable units For example byte vs word addressable For example byte vs word addressable Most machines are 8-bit byte addressable Most machines are 8-bit byte addressable Memory size Memory size Form of Addresses Form of Addresses Usually a simple linear address 0.. 2**N-1 Usually a simple linear address 0.. 2**N-1 But not always But not always

Data Formats We are interested in hardware support We are interested in hardware support Integer formats Integer formats Floating formats Floating formats Character Formats Character Formats Pointer/Address formats Pointer/Address formats Other types Other types

Integer Formats Sizes supported (1,2,4,8 byte) Sizes supported (1,2,4,8 byte) Unsigned vs Signed Unsigned vs Signed Signed format (usually twos complement) Signed format (usually twos complement) Little-endian vs Big-endian Little-endian vs Big-endian Little-endian has least significant byte at lowest address Little-endian has least significant byte at lowest address Big-endian has most significant byte at lowest address. Big-endian has most significant byte at lowest address. May have dynamic/static switching May have dynamic/static switching

More on Endianness: An Example Suppose we have the integer 258 in decimal Suppose we have the integer 258 in decimal Hex value (16 bits) is 0102h Hex value (16 bits) is 0102h Suppose machine is byte addressable Suppose machine is byte addressable Value is stored at addresses 1000h and 1001h Value is stored at addresses 1000h and 1001h Little endian: Little endian: 1000h: 02h 1000h: 02h 1001h: 01h 1001h: 01h Big endian: Big endian: 1000h: 01h 1000h: 01h 1001h: 02h 1001h: 02h

Floating Formats Complex possibilities Complex possibilities Most machines use “IEEE” formats Most machines use “IEEE” formats IEEE = IEEE standard 754/854 IEEE = IEEE standard 754/854 Provides 32- and 64-bit standard formats Provides 32- and 64-bit standard formats Also implementation dependent larger format Also implementation dependent larger format On Intel, this is 80-bits On Intel, this is 80-bits To be addressed separately To be addressed separately

Character Formats Common character codes Common character codes ASCII (7-bit) ASCII (7-bit) ISO Latin-1 (8 bit) ISO Latin-1 (8 bit) PC codes (several possibilities) PC codes (several possibilities) Unicode (16-bit) Unicode (16-bit) Machines usually do not have any specific hardware that cares what code you use Machines usually do not have any specific hardware that cares what code you use

Pointer/Address Formats Used to hold address of memory location Used to hold address of memory location Usually but not always simple unsigned integer, using same operations Usually but not always simple unsigned integer, using same operations But on some machines, segmented forms are used (to be examined later) But on some machines, segmented forms are used (to be examined later)

Other Formats Remember we are talking hardware here Remember we are talking hardware here Packed decimal Packed decimal Two decimal digits stored in one byte Two decimal digits stored in one byte For example 93 stored as hexadecimal 93 For example 93 stored as hexadecimal 93 Used by COBOL programs Used by COBOL programs Fractional binary Fractional binary For example with binary point at left For example with binary point at left h = 0.5 (unsigned) h = 0.5 (unsigned) Special graphics/multimedia formats Special graphics/multimedia formats Vector/array processing Vector/array processing

Data Alignment Consider address of a four byte integer. Consider address of a four byte integer. Said to be aligned if the address is a multiple of four bytes Said to be aligned if the address is a multiple of four bytes What happens if data is misaligned What happens if data is misaligned Works, but slower. How much slower? Works, but slower. How much slower? Fatal error, not recoverable Fatal error, not recoverable Error, but software recoverable (slow!) Error, but software recoverable (slow!)

General Register Structure How many registers? How many registers? How many bits How many bits What data can be stored? What data can be stored? Special purpose vs General purpose Special purpose vs General purpose Special purpose registers used only by certain instructions (e.g. ECX for loops on ia32) Special purpose registers used only by certain instructions (e.g. ECX for loops on ia32) General purpose registers fully interchangable General purpose registers fully interchangable

Specialized Registers Flag registers Flag registers System registers (e.g. state of floating- point unit) System registers (e.g. state of floating- point unit) Debug and control registers Debug and control registers Special registers for handling interrupts Special registers for handling interrupts Special registers for special instructions Special registers for special instructions

Instruction Set What set of operations are available What set of operations are available What memory reference instructions What memory reference instructions Load/Store only vs more extensive Load/Store only vs more extensive What operations between registers What operations between registers How are flags set etc How are flags set etc

Addressing Modes Direct addressing (address in instruction) Direct addressing (address in instruction) No room in RISC design for 32 bit address in a 32 bit instruction, so often not available. No room in RISC design for 32 bit address in a 32 bit instruction, so often not available. Indirect through register (simple indexing) Indirect through register (simple indexing) Available on all machines. Quite general since all of the instruction set can be used to compute the needed address. Available on all machines. Quite general since all of the instruction set can be used to compute the needed address. Other addressing modes Other addressing modes

Other Addressing Modes Index + Offset (offset in the instruction) Index + Offset (offset in the instruction) Common, offset is small (8-16 bits) Common, offset is small (8-16 bits) Used to reference locations on stack frame Used to reference locations on stack frame Used to reference fields in structure Used to reference fields in structure Double indexing (two regs added) Double indexing (two regs added) Double indexing + offset Double indexing + offset Scaling (register multipled by 2,4,8 …) Scaling (register multipled by 2,4,8 …) Fancier indirect modes Fancier indirect modes

Instruction Formats How many different instruction formats How many different instruction formats Fixed vs Variable size instructions Fixed vs Variable size instructions Uniform vs non-uniform formats Uniform vs non-uniform formats Size of instructions Size of instructions

Instruction Level Parallelism Can instructions execute in parallel Can instructions execute in parallel If so, is this If so, is this Invisible to programmer Invisible to programmer Instructions executed as though in strict sequence Instructions executed as though in strict sequence Visible to programmer Visible to programmer Programmer must be aware of parallelism Programmer must be aware of parallelism Specific special cases Specific special cases For example, branch delay slots For example, branch delay slots

Branch Delay Slots On some machines, instructions are basically executed in sequence, except for jumps, where we have: On some machines, instructions are basically executed in sequence, except for jumps, where we have: mov... mov … jmp … mov … mov... mov … jmp … mov … Third mov instruction is executed BEFORE the jump instruction. Third mov instruction is executed BEFORE the jump instruction.

Traps and Interrupts Terminology varies Terminology varies We will use the terms this way We will use the terms this way Traps are the immediate synchronous result of a particular instruction, for example, a trap caused by a division by zero Traps are the immediate synchronous result of a particular instruction, for example, a trap caused by a division by zero Interrupts happen asynchronously because of external events, e.g. an I/O interrupt Interrupts happen asynchronously because of external events, e.g. an I/O interrupt

Traps What instructions cause traps What instructions cause traps Are traps strictly synchronous? Are traps strictly synchronous? Or is this a place where pipelines become potentially visible Or is this a place where pipelines become potentially visible How does machine handle trap How does machine handle trap

Interrupts How are external interrupts handled How are external interrupts handled Multiple levels of interrupts Multiple levels of interrupts Interrupt priorities Interrupt priorities Mechanisms for handling interrupts Mechanisms for handling interrupts

Modes of Operation Kernel/supervisor/system mode vs application/program mode Kernel/supervisor/system mode vs application/program mode Or more fancy schemes (e.g. four levels in ia32 architectures), rings of protection. Or more fancy schemes (e.g. four levels in ia32 architectures), rings of protection. What instructions are disallowed when? What instructions are disallowed when? How does operation switch from one mode to another? How does operation switch from one mode to another?

Handling of I/O Input/Output Instructions Input/Output Instructions Input/Output Channels Input/Output Channels Interaction with processing modes Interaction with processing modes Interrupt handling Interrupt handling

Memory Handling All machines we look at have virtual addressing capabilities. All machines we look at have virtual addressing capabilities. This is a system for mapping from virtual addresses to physical addresses This is a system for mapping from virtual addresses to physical addresses Handled by hardware/software? Handled by hardware/software? What algorithms are used? What algorithms are used? Interaction with system modes Interaction with system modes

Caching Issues Mostly a matter of implementation rather than architecture. Mostly a matter of implementation rather than architecture. But caching may be visible to software But caching may be visible to software For example, instructions that bypass the cache. For example, instructions that bypass the cache.

Parallel Processing Issues Consider building machine with more than one processor Consider building machine with more than one processor What help from hardware? What help from hardware? Synchronization Synchronization Cache coherency Cache coherency Shared vs separate memory Shared vs separate memory Message processing Message processing How is shared memory handled? How is shared memory handled?

MP - Synchronization How do processors communicate How do processors communicate Shared memory Shared memory Special locking instructions Special locking instructions Message passing Message passing

MP – Cache Coherency Suppose multiple processors share a common memory. Suppose multiple processors share a common memory. Each processor has a cache Each processor has a cache What happens if one processor changes memory What happens if one processor changes memory Other processor may have old data in the cache (like what happens with internet browsers sometimes) Other processor may have old data in the cache (like what happens with internet browsers sometimes)

MP: Shared vs Separate Memory Many processors may share same memory Many processors may share same memory If they do, how are conflicts resolved If they do, how are conflicts resolved For example, order of stores and loads For example, order of stores and loads Or each processor may have separate local memory Or each processor may have separate local memory

MP: Message Passing Typical MP systems have some way of passing messages between processors. Typical MP systems have some way of passing messages between processors. This could just be in software using standard I/O facilities This could just be in software using standard I/O facilities Or there might be special hardware for the purpose Or there might be special hardware for the purpose

Implementation Issues Does architecture assume specific implementation details Does architecture assume specific implementation details Scheduling Scheduling Caching Caching Pipelining Pipelining

Compiler Issues How is code generated for this machine? How is code generated for this machine? Any special problems? Any special problems? Any special features designed to make translation of specific features easier? Any special features designed to make translation of specific features easier?

Operating Systems Issues How is an Operating System for this machine constructed? How is an Operating System for this machine constructed? Any special problems Any special problems Any special features designed to make the life of an OS easier? Any special features designed to make the life of an OS easier? For example, special instructions for task swiching, state saving, multiple processes accessing virtual memory etc. For example, special instructions for task swiching, state saving, multiple processes accessing virtual memory etc.

End of Lecture See you next Tuesday See you next Tuesday Send any problems to class list Send any problems to class list (see class page for how to sign up) (see class page for how to sign up) Assignment: send one message to class list Assignment: send one message to class list Either an interesting question, or just hello! Either an interesting question, or just hello! These slides will be up on the Web in HTML and Power point formats These slides will be up on the Web in HTML and Power point formats