Intel Microprocessor Features Pentium  IIPentium  IIIPentium  4 MPR Issue June 1997April 2000Dec 2001 Clock Speed 266 MHz1GHz2GHz Pipeline Stages 12/14.

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Presentation transcript:

Intel Microprocessor Features Pentium  IIPentium  IIIPentium  4 MPR Issue June 1997April 2000Dec 2001 Clock Speed 266 MHz1GHz2GHz Pipeline Stages 12/14 22/24 Transistors 7.5M24M42M Cache (I/D/L2) 16k/16K/-16K/16K/256K12K/8K/256K Die Size 203mm 2 106mm 2 217mm 2 IC Process 0.28  m, 4M0.18  m, 6M Max Power 27W23W67W

Clock distribution network with deskewing circuit (Geannopoulos and Dai 1998), Copyright © 1998 IEEE

Delay shift register (Geannopoulos and Dai 1998), Copyright © 1998 IEEE

Phase detector (Geannopoulos and Dai 1998), Copyright © 1998 IEEE

Clock distribution topology (Rusu and Tam 2000), Copyright © 2000 IEEE

Deskew buffer architecture (Rusu and Tam 2000), Copyright © 2000 IEEE

Digitally controlled delay line (Rusu and Tam 2000), Copyright © 2000 IEEE

Simulated regional clock-grid skew (Rusu and Tam 2000), Copyright © 2000 IEEE

Measured regional clock skew (Rusu and Tam 2000), Copyright © 2000 IEEE

Core and I/O clock generation (Kurd et al. 2001), Copyright © 2001 IEEE

Logical diagram of core clock distribution (Kurd et al. 2001), Copyright © 2001 IEEE

Example of local clock buffers generating various frequency, phase and types of clocks (Kurd et al. 2001), Copyright © 2001 IEEE

UltraSPARC Family Characteristics UltraSPARC-IUltraSPARC-IIUltraSPARC-III Year ArchitectureSPARC V9, 4-issue Die size17.7x17.8mm x12.5mm 2 15x15.5mm 2 # of transistors5.2M5.4M23M Clock Frequency167MHz330MHz1GHz Supply voltage3.3V2.5V1.6V Process 0.5  m CMOS0.35  m CMOS0.15  m CMOS Metal layers4 (Al)5 (Al)7 (Al) Power consumption<30W <80W

Clock distribution delay in UltraSPARC-III (Heald et al. 2000), Copyright © 2000 IEEE

Semidynamic flip-flop (Klass 1998), Copyright © 1998 IEEE

(a)Logic embedding in a semidynamic flip-flop; (b)Two-input XOR function. (Klass, 1998), Copyright © 1998 IEEE

Dynamic versions of semidynamic flip-flop: single-ended; Differential. (Klass 1998), Copyright © 1998 IEEE

UltraSPARC-III flip-flop (Heald et al. 2000), Copyright © 2000 IEEE

Alpha Microprocessor Features # transistors Die Size [mm 2 ] 16.8x x x x18.8 Process 0.75  m0.5  m0.35  m0.18  m Supply [V] Power [W] Clk. Freq. [MHz] Gates/Cycle

Alpha microprocessor final clock driver location: (a) 21064, (b) 21164, (c) (a)(b)(c)

21064 clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE

21164 clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE

21264 clock hierarchy (Gronowski et al. 1998), Copyright © 1998 IEEE

21264 clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE

21364 major clock domains (Xanthopoulos et al. 2001), Copyright © 2001

21364, NCLK clock skew (Xanthopoulos et al. 2001), Copyright © 2001 IEEE

21064 modified TSPC latches (Gronowski et al. 1998), Copyright © 1998

21164: (a) phase-A latch, (b) phase-B latch (Gronowski et al. 1998), Copyright © 1998 IEEE (a)(b)

Embedding of logic into a latch: (a) TSPC latch, one level of logic; (b) latch, two levels of logic. (Gronowski et al. 1998), Copyright © 1998 IEEE (a)(b)

21264 flip-flop (Gronowski et al. 1998), Copyright © 1998 IEEE

Critical-path and race analysis for clock buffering and conditioning (Gronowski et al. 1998), Copyright © 1998 IEEE

Hazard-free level-sensitive polarity-hold latch

General LSSD configuration

LSSD shift register latch

LSSD double-latch design

LSSD SRL with multiplexer used in the IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission

Static multiplexer version of the SRL used in the IBM S/390 G4 (Sigal et al. 1997), reproduced by permission

A clocked storage element is used in the non-timing-critical timing macros of the IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission

The clock-generation element used to detect problems created with fast paths: IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission

The experimental IBM PowerPC processor (Silberman et al. 1998), reproduced by permission

The PowerPC 603 MSL (Gerosa et al. 1994), Copyright © 1994 IEEE

The PowerPC 603 local clock regenerator (Gerosa et al. 1994), Copyright © 1994 IEEE

IBM Power4 TM 64-bit processor used in IBM eServer p690. The microprocessor consists of 174 million transistors and runs at 1.3 GHz, contains two microprocessor cores, and an on- chip memory subsystem. It is fabricated in state-of-the-art IBM 0.18  CMOS SOI technology with seven levels of copper wiring (Warnock et al. 2002), reproduced by permission

Standard transmission-gate MSL with LSSD capability (Warnock et al. 2002), reproduced by permission

Scannable split latch with LSSD capability used in the IBM Power4 TM. Designers were allowed to tune transmission gate size and specify input and output gates (Warnock et al. 2002), reproduced by permission

Library MSL with integrated front-end logic gate choices (Warnock et al. 2002), reproduced by permission

Split-latch designs with integrated front- and back-end logic-gate choices (Warnock et al. 2002), reproduced by permission