Dept. of ECE, GMU ECE Registers and Memory Access Dr. Qiang Lin

Dept. of ECE, GMU ECE General Purpose Registers 8 bit registers do not form an independent register set –Modifying al will change the value of ax; so will modifying ah. The value of al exactly corresponds to bits 0 through 7 of ax. The value of ah corresponds to bits 8 through 15 of ax. –Modifying ax will change both al and ah. –Changing al will not affect the value of ah, and vice versa –The above applies to bx/bl/bh, cx/cl/ch, and dx/dl/dh as well

Dept. of ECE, GMU ECE Flags Register Unlike other registers it is simply a set of one bit values which help determine current CPU state and condition codes

Dept. of ECE, GMU ECE Extra Registers Added protected mode operation above 8086 –Will not cover this because it was poorly designed and it is of interest only to programmers who are writing their own operating system or low-level systems programs for such operating systems 3 additional bits in flags register –I/O Privilege Level is a two bit value (bits 12 and 13) to specify 4 privilege levels to perform I/O operations –NT flag controls operation of an interrupt return

Dept. of ECE, GMU ECE Extra Registers (contiuned) 5 more registers used by OS to support memory management and multiple processes –machine status word (msw) –global descriptor table register (gdtr) –local descriptor table register (ldtr) –interrupt descriptor table register (idtr) and –task register (tr)

Dept. of ECE, GMU ECE In addition to all registers on 80286, added several new registers and extended definition of existing registers Rename new 32 bit registers to differentiate them from their 16 bit versions as: –eax, ebx, ecx, edx, esi, edi, ebp, esp, eflags, and eip Added two 16 bit segment registers - fs and gs –Programmer can access up to 6 segments simultaneously –All segment registers are still 16 bits and were not extended to 32 bits as the other registers Registers

Dept. of ECE, GMU ECE Registers (continued) Extended flag register to 32 bit and defined 2 more bits –Bit 16 as debug resume flag (RF) used with set of debug registers –Bit 17 for Virtual 8086 mode flag (VM) to determine whether processor is running in virtual-86 mode (simulating 8086) or standard protected mode Added 4 control registers –CR0-CR3, control functions such as paged memory management, protected mode operation, and more

Dept. of ECE, GMU ECE Registers (continued) Added a set of test registers –Allow system to test the proper operation of the processor when the system powers up –Allow testing immediately after manufacture Added eight debugging registers –Microsoft Codeview or Turbo Debugger can use these registers to set breakpoints when you are trying to locate errors within a program –While not using these registers in an application program, they will reduce the time it takes to eradicate bugs from programs. –Debuggers accessing these registers will only function properly on or later processor

Dept. of ECE, GMU ECE and Pentium Registers Did not add any new registers to 80386's basic register set Defined eflags register Bit 18 as alignment check flag –Along with CR0, force a trap (program abort) whenever processor accesses non-aligned data (e.g., a word on an odd address or a double word at an address which is not an even multiple of four) Defined new functions using CR0-CR3 for cache enable/disable/operation, which are not on 80386

Dept. of ECE, GMU ECE , and Pentium Registers

Dept. of ECE, GMU ECE Sgemented Addressing Use two components to specify a memory location –A segment value and an offset within that segment –Can be viewed as 2-d array with segment provides one dimension into the array and offset provides the other

Dept. of ECE, GMU ECE Compute 8086 Physical Address Simple process - multiply segment value by 10h and then add offset –For example, consider the segmented address: 1000:1F00 Multiply segment value (1000h) by 10h, i.e., just append a zero to the end to 10000h Add 1F00h to this to obtain 11F00h, which is the physical address

Dept. of ECE, GMU ECE Compute or Better Physical Address and later processors introduced protected mode segments and use a look up table to compute physical address –Use segment value as index into an array. The contents of the selected array element provide starting address for the segment –The CPU adds this value to the offset to obtain the physical address –Applications cannot directly modify segment descriptor table (lookup table); protected mode OS (UNIX, Linux, Windows, OS/2) handles it

Dept. of ECE, GMU ECE Normalized Addresses When operating in real mode, a problem develops –A single object in memory may be mapped using several different addresses –For example, 1000:1F00 may be mapped as 11F0:0, 1100:F00, and even 1080:1700, all point to physical address 11F00h Solution - normalized addresses –Unless two normalized segmented values are exactly the same, they do not point at the same object in memory A normalized address defined as follows: –Segment portion of the address may be any 16 bit value, but offset portion must be a value in range 0..0Fh –Convert segmented address to PA. Then slap a colon between last two digits of five-digit result as 1000:1F00 -> 11F00 -> 11F0:0 for 80x86 processors in real mode only

Dept. of ECE, GMU ECE Displacement Only Addressing Mode Most common and easiest to understand Consists of a 16 bit constant that specifies the address of the target location –Instruction mov al,ds:[8088h] loads al register with a copy of the byte at memory location 8088h

Dept. of ECE, GMU ECE Register Indirect Addressing Modes Access memory indirectly through a register –For example, mov al, ds:[bx] or mov al, ss:[si]

Dept. of ECE, GMU ECE Indexed Addressing Modes Use the following syntax: mov al, disp[bx] or mov al, cs:disp[si] For examples –If bx contains 1000h, instruction mov cl,20h[bx] will load cl from memory location ds:1020h –Likewise, if bp contains 2020h, mov dh,1000h[bp] will load dh from location ss:3020

Dept. of ECE, GMU ECE Based Indexed Addressing Modes Combinations of register indirect addressing modes Form offset by adding a base register (bx or bp) and an index register (si or di) in form of mov al, [bx][si] Let bx contains 1000h and si contains 880h, the above instruction will load al from location DS:1880h

Dept. of ECE, GMU ECE Based Indexed Plus Displacement Addressing Mode Slight modification of base/indexed addressing modes with addition of an 8 bit or 16 bit constant

Dept. of ECE, GMU ECE Addressing Modes Generalized memory addressing modes –Whereas 8086 is only allowed to use bx or bp as base registers and si or di as index registers, is allowed use almost any general purpose 32 bit register as a base or index register –Furthermore, introduced new scaled indexed addressing modes to simplify accessing array elements

Dept. of ECE, GMU ECE Register Indirect Addressing Modes May specify any general purpose 32 bit register –[eax], [ebx], [ecx], [edx], [esi], and [edi] all provide offsets, by default, into data segment –The [ebp] and [esp] addressing modes use stack segment by default While running in 16 bit real mode, offsets in these 32 bit registers must still be in the range 0...0FFFFh –Cannot use values larger to access more than 64K in a segment Must use 32 bit register names, not 16 bit names

Dept. of ECE, GMU ECE Indexed, Base/Indexed, and Base/Indexed/Disp Addressing Modes When combining two 32 bit registers in an addressing mode, the 1 st register is base register and the 2 nd register is index register –True regardless of the register names mov al, disp[edx+ebp] ;Uses DS by default mov al, [esi][edi][disp] mov al, [edi][disp][esi] mov al, disp[ebp+ebx] ;Uses SS by default Except for one restriction –Cannot use esp register as an index register, but OK as base

Dept. of ECE, GMU ECE Scaled Indexed Addressing Modes The indexed, base/indexed, and base/indexed/disp addressing modes are special cases of scaled indexed addressing modes, which –Particularly useful for accessing elements of arrays –Allow to multiply index register in addressing mode by 1, 2, 4, or 8 as disp[base][index*n] For example, ebx contains 1000h and esi contains 4, then mov al,8[ebx][esi*4] ;Loads AL from location 1018h mov al,1000h[ebx][ebx*2] ;Loads AL from location 4000h mov al,1000h[esi*8] ;Loads AL from location 1020h

Dept. of ECE, GMU ECE Addressing Modes Summary Addressing modes are more orthogonal so much easier to memorize than 8086's addressing modes Problem: For programmers working on 80386, there is always temptation to skip 8086 addressing modes and use set exclusively –However, 8086 addressing modes really are more efficient than comparable addressing modes –Therefore, important to know all addressing modes and choose appropriate one to the problem at hand

Dept. of ECE, GMU ECE Which is Index Register If use scaled index operator ("*n") on a register, that register is always index register regardless of where it appears in the addressing mode such as: [ebp*1][ebx] ;Uses DS by default [ebx][ebp*1] ;Uses DS by default [ebp][ebx*1];Uses SS by default [ebx*1][ebp];Uses SS by default es:[ebx][ebp*1] ;Uses ES.

Dept. of ECE, GMU ECE MOV Instruction Syntax as: mov Dest, Source Take only 3 forms as: –mov reg, memory –mov memory, reg –mov reg, reg Missing - mov memory, memory –Not supported! –Loading a register and then storing that register is almost always more efficient

Dept. of ECE, GMU ECE MOV Instruction (continued) Many different mov instructions can accomplish the same thing Several different addressing modes can access the same memory location If interested in writing the shortest and fastest possible programs in assembly language, must be constantly aware of trade-offs between equivalent instructions!