Processor Function Topic 3

After studying this chapter you should be able to - describe the structure of typical assembly language instructions using the terms op-code and operand describe and give examples of assembly language instructions of the following types data transfer arithmetic logical shift and rotate branch

B Revision Question 1 Machine code is a common programming language which can be used on any machine the low level language specific to a particular microprocessor the number which identifies a particular type of computer any high level language which can be compiled for use by a microprocessor B

Revision Question 2 The processor register which holds the address of the next instruction to be fetched is the memory address register (MAR) instruction register (IR) program counter (PC) memory data register (MDR) C

Revision Question 3 The correct sequence of steps in the fetch-execute cycle is fetch instruction ➜ increment PC ➜ decode instruction ➜ execute instruction increment PC ➜ fetch instruction ➜ decode instruction ➜ execute instruction fetch instruction ➜ decode instruction ➜ increment PC ➜ execute instruction fetch instruction ➜ decode instruction ➜ execute instruction ➜ increment PC A

D Revision Question 4 Data fetched from memory arrives in the memory address register (MAR) the instruction register (IR) the program counter (PC) the memory data register (MDR) D

B Revision Question 5 In an 8-bit microprocessor, the data and address buses must both be 8 bits wide the data bus is 8 bits wide, but the address bus may be more than 8 bits wide the address bus must be 8 bits wide, but the data bus can be any width a single 8 bit wide system bus is used to transfer all data and addresses B

Machine Code Processors only understand instructions in machine code These are difficult to read and understand e.g 10101001 00000001 10000101 01110000 10100101 01110000

Machine Code Assembly Language 10101001 00000001 10001101 00000011 10101001 00000001 10001101 00000011 11101000 01101001 00000001 11101001 00100000 11101110 11111111 01100000 LDA #1 STA 1000 LDA 1000 ADC #1 STA 1001 JSR OSWRCH RTS Mnemonic – a short code – replaces the machine code instruction

Assembly Language Instructions Op-code Operand What the instruction is to do Data to be operated upon

Assembly Language Instructions Op-code Operand Meaning LDA #1 Load the accumulator with the value 1 STA 1DFF Store the contents of the acc in memory location 1DFF LDA 3C15 Load the acc. with the contents of memory location 3C15

Assembly Language Instructions Op-code Operand LDA #1 10101001 00000001

Machine Code Assembly Language 10101001 00000001 10001101 00000011 10101001 00000001 10001101 00000011 11101000 01101001 00000001 11101001 00100000 11101110 11111111 01100000 LDA #1 STA 1000 LDA 1000 ADC #1 STA 1001 JSR OSWRCH RTS

Instruction Formats Not all instructions are the same length e.g. 6502 processor– 8-bit Op-code 8-bit Op-code 8-bit operand 8-bit Op-code 16-bit operand

Instruction Formats IBM mainframe instruction set 8-bit Op-code 4-bit operand 4-bit operand 8-bit Op-code 4-bit operand 4-bit operand 12-bit operand

Instruction Formats X86 mainframe instruction set

Assembly Language Instructions Regardless of processor, all instructions the same format - Op-code Operand What the instruction is to do Data or address of data to be operated upon

Instruction types Data transfer instructions Arithmetic instructions Logical instructions Shift and rotate instructions Branch

Data transfer Used to move data from one place to another Between registers From memory to processor/register From processor to memory

Arithmetic Used to carry out simple arithmetic e.g. +-/x Add contents of 2 registers Adding 1 to contents of register

Logical Used to make logical comparisons Checking whether contents of two registers are equal to each other

Shift and rotate Used to manipulate the individual bits within a register Shift left 1 bit

Branch Branch instructions break the normal sequential flow of execution by changing the program counter if a specified condition is met.

6502 processor Simple processor used in BBC, Apple II and Atari

6502 Microprocessor System

6502 Microprocessor System introduced in about 1975 among the first microprocessors to be used in early home computers. included the usual Arithmetic/Logic Unit with some internal registers and a Control Unit all on the same chip. It had an external crystal-controlled clock to generate timing signals

6502 Microprocessor System ROM was used to hold a bootstrap program to permit initial operation of the system RAM was used to hold programs and data The interface with the external devices was via a Programmable Input/Output unit (PIO), which communicated with the external devices using 16-bit wide I/O buses.

6502 Microprocessor System The external bus was a combination of an 8-bit-wide data bus, a 16-bit-wide address bus and some control lines that carried synchronisation signals throughout the system.

6502 Microprocessor System Hence only 8 bits of data could be moved around the system, but 16-bit addresses could be used to address memory. Memory locations with addresses in the range 0 to 65535 (216-1) could be directly addressed Memory was made up of individually addressable 8-bit words (bytes).

6502 Microprocessor System - registers 8 bits – used for storing data 16 bits – used for storing 16 bit addresses

6502 Registers 8 bit registers A X Y SR IR MDR 16-bit registers MAR PC SP

6502 registers - A A is known as the Accumulator – the main general purpose register in which data is held during most arithmetical and logical operations

6502 registers – X,Y X and Y are index registers. They are designed to hold loop counters or as gp registers

6502 registers - SR SR is the status register. It is really a set of 8 1-bit registers. Each bit operates independently, and is used to flag to record the status of the processor after each instruction

6502 registers - SR N- the negative flag – set o 1 if the result of the last operation is zero V – the overflow flag – set to 1 if the last result operation is invalid B – the break bit – set to 1 when a break instruction is executed D – the decimal flag – when set to 1, the processor will operate using binary coded decimal arithmetic I – the interrupt disable flag – when set the processor will ignore any interrupt signals Z – the zero flag – set to 1 when the last result was zero C – the carry flag – set to 1 if the result of an operation is a number that cannot be stored in a single 8-bit register

6502 registers - IR IR is the instruction register. It holds the instruction being decoded or executed

6502 registers - MDR MDR is the Memory Data register. It holds data which has just arrived along the data bus or is just about to be sent along the data bus

6502 registers - MAR MAR is the Memory Address register. It holds an address about to be sent out along the address bus

6502 registers - PC PC is the Program Counter. It holds the address of the next instruction to be fetched, decoded and executed

6502 registers - SP SP is the Stack Pointer. Temporary data storage. The SP holds the address of the next free location in the stack

Exercise Copy and complete the table Page 55 Q.7 Complete questions 8-11

LDA #55 Load the accumulator with the value 55 See scholar animation

Addressing Modes Refers to the operand There are many types e.g. Immediate Direct Implied Others such as relative, indirect, indexed

Immediate Addressing The operand is the actual data to be used Example – LDA #55 Other examples CMP #27 – compare the contents of A with the number 27 LDX #A4 – load the X register with the value A4 LDY #00 – load the Y register with the number 00 8-bit Op-code 8-bit operand

Direct Addressing The operand is the address to be used Example – LDA 3C15 Other examples JMP 2015 – jump to instruction in location 2015 ADC 2099 – add the data in location 2099 to the accumulator 8-bit Op-code 16-bit operand (address)

Implied Addressing No operand is required Example – TAX – transfer the contents of A to X Other examples TYA – transfer the contents of the Y-register to the accumulator 8-bit Op-code

Other addressing modes As well as immediate, absolute and implied addressing, the 6502 processor has many other addressing modes. These include: relative addressing - for example BEQ 09, which means "if the zero flag was set by the last operation, branch to the instruction 9 locations forward in memory" indexed addressing - for example LDA 3C15,Y which means "load the accumulator with the data to be found at the location 3C15+Y, where Y is the value stored in the Y register indirect addressing - for example LDA (3C15), which means "load the accumulator with the data you find at the address which is to be fond at location 3C15"

Instruction types Data transfer instructions Arithmetic instructions Logical instructions Shift and rotate instructions Branch instructions Various others Now have a look at the animations in Scholar

Program 1 – adding two numbers CLC clear the carry flag, just in case LDA 2004 fetch the number from location 2004 ADC 2005 add on the number from location 2005 STA 2006 store the result in location 2006

Program 2 – Multiplying by 3 CLC clear the carry flag, just in case LDA 2004 fetch the number from location 2004 ADC 2004 add the number to itself ADC 2004 add the number on again STA 2005 store the result in location 2005

Program 3 – Multiplying two numbers LDA 2004 fetch the number from location 2004 LDX 2005 load the X register with the number from location 2005 DEX reduce X by 1 (see note 1 below) CLC clear the carry flag just in case ADC 2004 add the number from location 2004 to the current value in the accumulator DEX reduce the X register by 1 BNE -6 if X is not zero, branch back 6 locations see note 2 below) STA 2006 store the result in location 2006

Exercise Scholar Page 91 Past Papers Q 12 – 19 2008 Q14 a-b 2006 Q17 b+c 2010 Q15 2011 Q11