Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, 20021 Thermal-Scheduling For Ultra Low Power Mobile Microprocessor George Cai 1 Chee.

Slides:



Advertisements
Similar presentations
Computer Structure Power Management Lihu Rappoport and Adi Yoaz Thanks to Efi Rotem for many of the foils.
Advertisements

CS 7810 Lecture 4 Overview of Steering Algorithms, based on Dynamic Code Partitioning for Clustered Architectures R. Canal, J-M. Parcerisa, A. Gonzalez.
Performance, Energy and Thermal Considerations of SMT and CMP architectures Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron Dept. of Computer Science,
Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors Abhishek Bhattacharjee Margaret Martonosi.
Keeping Hot Chips Cool Ruchir Puri, Leon Stok, Subhrajit Bhattacharya IBM T.J. Watson Research Center Yorktown Heights, NY Circuits R-US.
Aleksandra Tešanović Low Power/Energy Scheduling for Real-Time Systems Aleksandra Tešanović Real-Time Systems Laboratory Department of Computer and Information.
Bypass Aware Instruction Scheduling for Register File Power Reduction Sanghyun Park 2 Aviral Shrivastava 1 Nikil Dutt 1 Alex Nicolau 1 Yunheung Paek 2.
June 20 th 2004University of Utah1 Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors Karthik Ramani Naveen Muralimanohar.
CS 7810 Lecture 12 Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors D. Brooks et al. IEEE Micro, Nov/Dec.
Chapter 17 Parallel Processing.
Chapter 1 and 2 Computer System and Operating System Overview
September 28 th 2004University of Utah1 A preliminary look Karthik Ramani Power and Temperature-Aware Microarchitecture.
Techniques for Efficient Processing in Runahead Execution Engines Onur Mutlu Hyesoon Kim Yale N. Patt.
CSE477 L26 System Power.1Irwin&Vijay, PSU, 2002 Low Power Design in Microarchitectures and Memories [Adapted from Mary Jane Irwin (
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving Zhiyuan He 1, Zebo Peng 1, Petru Eles 1 Paul Rosinger 2, Bashir M. Al-Hashimi.
Temperature-Aware Design Presented by Mehul Shah 4/29/04.
Power-Aware Computing 101 CS 771 – Optimizing Compilers Fall 2005 – Lecture 22.
Author: D. Brooks, V.Tiwari and M. Martonosi Reviewer: Junxia Ma
Power-aware Computing n Dramatic increases in computer power consumption: » Some processors now draw more than 100 watts » Memory power consumption is.
Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors Nikolaos Bellas, Ibrahim N. Hajj, Fellow, IEEE, Constantine.
CS 423 – Operating Systems Design Lecture 22 – Power Management Klara Nahrstedt and Raoul Rivas Spring 2013 CS Spring 2013.
Slide 1 U.Va. Department of Computer Science LAVA Architecture-Level Power Modeling N. Kim, T. Austin, T. Mudge, and D. Grunwald. “Challenges for Architectural.
1 Copyright © 2012, Elsevier Inc. All rights reserved. Chapter 1 Fundamentals of Quantitative Design and Analysis Computer Architecture A Quantitative.
Erkan Çetiner. Outline Introduction Related Works Modeling Methodology Baseline Results DTM Techniques Conclusions.
Low Power Techniques in Processor Design
Lecture 03: Fundamentals of Computer Design - Trends and Performance Kai Bu
Low-Power Wireless Sensor Networks
1 Overview 1.Motivation (Kevin) 1.5 hrs 2.Thermal issues (Kevin) 3.Power modeling (David) Thermal management (David) hrs 5.Optimal DTM (Lev).5 hrs.
1 Using Multiple Energy Gears in MPI Programs on a Power- Scalable Cluster Vincent W. Freeh, David K. Lowenthal, Feng Pan, and Nandani Kappiah Presented.
Sogang University Advanced Computing System Chap 1. Computer Architecture Hyuk-Jun Lee, PhD Dept. of Computer Science and Engineering Sogang University.
1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
Critical Power Slope Understanding the Runtime Effects of Frequency Scaling Akihiko Miyoshi, Charles Lefurgy, Eric Van Hensbergen Ram Rajamony Raj Rajkumar.
Probabilistic Preemption Control using Frequency Scaling for Sporadic Real-time Tasks Abhilash Thekkilakattil, Radu Dobrin and Sasikumar Punnekkat.
MS108 Computer System I Lecture 2 Metrics Prof. Xiaoyao Liang 2014/2/28 1.
C OMPUTER O RGANIZATION AND D ESIGN The Hardware/Software Interface 5 th Edition Chapter 1 Computer Abstractions and Technology Sections 1.5 – 1.11.
1 Distributed Energy-Efficient Scheduling for Data-Intensive Applications with Deadline Constraints on Data Grids Cong Liu and Xiao Qin Auburn University.
Energy-Effective Issue Logic Hasan Hüseyin Yılmaz.
Thermal-aware Issues in Computers IMPACT Lab. Part A Overview of Thermal-related Technologies.
Chap 1 Introduction. What is OS? OS is a program that interfaces users and computer hardware. Purpose: Provides an environment for users to execute programs.
Bypass Aware Instruction Scheduling for Register File Power Reduction Sanghyun Park, Aviral Shrivastava Nikil Dutt, Alex Nicolau Yunheung Paek Eugene Earlie.
Houman Homayoun, Sudeep Pasricha, Mohammad Makhzan, Alex Veidenbaum Center for Embedded Computer Systems, University of California, Irvine,
Power Estimation and Optimization for SoC Design
VGreen: A System for Energy Efficient Manager in Virtualized Environments G. Dhiman, G Marchetti, T Rosing ISLPED 2009.
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multiprocessor Systems Zhiyi Yu, Bevan M. Baas VLSI Computation Lab, ECE department,
Software Architecture for Dynamic Thermal Management in Datacenters Tridib Mukherjee Graduate Research Assistant IMPACT Lab ( Department.
Lev Finkelstein ISCA/Thermal Workshop 6/ Overview 1.Motivation (Kevin) 2.Thermal issues (Kevin) 3.Power modeling (David) 4.Thermal management (David)
Critical Power Slope: Understanding the Runtime Effects of Frequency Scaling Akihiko Miyoshi †,Charles Lefurgy ‡, Eric Van Hensbergen ‡, Ram Rajamony ‡,
Runtime Software Power Estimation and Minimization Tao Li.
Hardware Architectures for Power and Energy Adaptation Phillip Stanley-Marbell.
Computer Science and Engineering Power-Performance Considerations of Parallel Computing on Chip Multiprocessors Jian Li and Jose F. Martinez ACM Transactions.
3/12/2013Computer Engg, IIT(BHU)1 INTRODUCTION-1.
11/15/05ELEC / Lecture 191 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
1 of 14 Lab 2: Design-Space Exploration with MPARM.
CS203 – Advanced Computer Architecture
1 Aphirak Jansang Thiranun Dumrongson
VU-Advanced Computer Architecture Lecture 1-Introduction 1 Advanced Computer Architecture CS 704 Advanced Computer Architecture Lecture 1.
Introduction to Performance Tuning Chia-heng Tu PAS Lab Summer Workshop 2009 June 30,
LOW POWER DESIGN METHODS
PipeliningPipelining Computer Architecture (Fall 2006)
Fall 2012 Parallel Computer Architecture Lecture 4: Multi-Core Processors Prof. Onur Mutlu Carnegie Mellon University 9/14/2012.
Overview Motivation (Kevin) Thermal issues (Kevin)
CS203 – Advanced Computer Architecture
Temperature and Power Management
Assembly Language for Intel-Based Computers, 5th Edition
Intel Atom Architecture – Next Generation Computing
A High Performance SoC: PkunityTM
The University of Adelaide, School of Computer Science
The University of Adelaide, School of Computer Science
Utsunomiya University
Presentation transcript:

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Thermal-Scheduling For Ultra Low Power Mobile Microprocessor George Cai 1 Chee How Lim 1 W. Robert Daasch 2 Intel Corporation 1 Integrated Circuit Design and Test Laboratory PSU 2

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Presentation Outline  Mobile CPU Power Efficiency With Demanded Performance  Thermal Scheduling For Mobile Microprocessor  Power Constrained Performance  Observations/Conclusions

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Ultra Low Power Mobile Microprocessor Primary pipeline: maximal performance, complex pipeline structure Second pipeline: Minimum power and energy consumption, very simple in order structure and target mobile anywhere-anytime applications. Transparent to OS and applications Maximal utilizing on die clock/power gating for energy saving FEDE EX RF DE IOP OOP Primary Secondary Majority mobile apps with performance requirements Text , caller-id, reminder and other none high performance w/ anywhere-anytime requested apps

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Low Energy Consumption With Providing Suitable Performance Is Key For “Anywhere And Anytime” Must be compatible with exist OS and platform Must have active leakage power control Must meet the real time telecom application requirements Stock/Urgent Messages Stock Update Alert Interactive command and reply All urgent message And important news News headline titles Calendar reminder Pages/voice message

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Runtime Thermal Scheduling Capability FEDE EX RF DE IOP OOP Primary Secondary When thermal threshold is exceeded, the pipeline clusters will service instructions in alternating manner: cool the “hot” pipeline by clock/power-gating & the “cold” pipeline sustains processor operations Flexible selecting the threshold point, the energy-delay product, performance, and reliability of the processor can be enhanced

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Thermal Effects: Leakage Trend Active leakage power reduction will be significant role for total power reduction Thermal control is important for low energy consumption for mobile CPU Derived from F. Pollack’s Micro-32 Keynote Presentation, 1999

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Example of Scheduling Algorithm S1: Normal Operation (Primary Pipeline) S2: Stall Fetch & Clear Pipeline S3: Alternate Operation (Secondary Pipeline) S4: Disable Clock or Scale F-V S1 S2 S3 T 1 < T H S4 T 1  T H T 1  T L T 1 > T L & T 2 < T H T 1 > T L & T 2  T H T 1 > T L || T 2 > T L T 1  T L & T 2  T L T S2 T S1 Temperature (  C) TaTa T max t cycle THTH t cool t heat Time (s) TLTL

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Enhance Effectiveness Of Other Power Control Techniques Dynamic Clock Disabling/Throttling Dynamic Frequency Scaling

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Power Constrained Clock Frequency With Performance Impact

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Thermal Effects on Power Divide total power into two components: dynamic and leakage power

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Thermal Effects on Energy Using power per frequency (W/MHz) metric as proxy for energy

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Architecture-Level Power-Performance Tradeoff For wide-superscalar processors, performance impact of pipeline scaling is smaller than global clock throttling or frequency scaling ~15% ~30%

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Comparative Outcomes: Energy Metric Simulation Conditions (500 million instructions; T L = 55  C) –Stop Clock Control: Toggle between F max and 0 MHz –Voltage/Freq Scaling: Toggle between F max and 0.9/0.8/0.6 F max –Thermal Scheduling: Toggle between Primary and 2nd Pipelines Clk gating V-F scaling Thermal scheduling M88KSIM LI GCC PERL Energy (J) Thermal Control Techniques Benchmarks Energy Consumption of Conservative Control M88KSIM LI GCC PERL Clk Gating F-V Scaling Thermal Scheduling M88KSIM LI GCC PERL Energy (J) Thermal Control Techniques Benchmarks Energy Consumption of Aggressive Control M88KSIM LI GCC PERL Conservative: T H = 70  C Aggressive: T H = 60  C

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Comparative Outcomes: Energy-CPU Time Metric Total Energy x CPU Time

Thermal-Scheduling For Ultra Low Power Mobile Microprocessor May, Pros and Cons Advantages Limits power/energy upper bound & prevents thermal runaway Pipeline tuned for either performance or ultra low power Existing OS and application compatible Performance penalty for engaging/disengaging control is small (architecture event) Supports low-power anywhere-anytime of mobile computing  Non-timing critical tasks  Real-time application that requires more predictable output Concerns  i/  t during pipeline switch Real-Register File may require extra dedicated ports Bypass bus may have additional loading