RLH - Spring 1998ECE 611 Hardware - 1 Basic Microprocessor Hardware ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department of Electrical and Computer Engineering Tennessee Technological University Spring 1998

RLH - Spring 1998ECE 611 Hardware - 2 Outline l Microprocessor Applications l Computer System Structure l Generic CPU, Memory, I/O l Specific Microprocessor Pinouts l Specific Microprocessor Timing

RLH - Spring 1998ECE 611 Hardware - 3 Introduction l Computer System - Hardware and Software l Typical Processors: –8086 Microprocessor –68000 Microprocessor –8051 Microcomputer or Microcontroller –Why different?

RLH - Fall 1997RLH - Spring 1998ECE 611 Hardware - 4 Applications of Microprocessors 2 Broad Applications: l General purpose computer –runs user programs –big memory, big peripherals –modular, complex, expandable l Embedded Computer –invisible to user –dedicated application, limited hardware –single board, less complex –our project and most designs

RLH - Spring 1998ECE 611 Hardware - 5 Basic Computer System CPU MEM I/O Peripherals Buses

RLH - Fall 1997RLH - Spring 1998ECE 611 Hardware - 6 Larger Computer System uP Buf & Ifc Buf RAM ROM CPU Memory Input/Output DATA ADDR CTL OPT IFC 1 IFC 2 IFC n Buf Dev 1 Dev 2 Dev n SYSTEM BUSES (related signals) l 1 board or multiple boards l DATA = info l ADDRESS= select src/dest item l CONTROL= timing l Buffers and inteface - why? Device-specific Interfaces and signals

RLH - Fall 1997RLH - Spring 1998ECE 611 Hardware - 7 Generic CPU Clock & Reset uP Addr Data clk rst Am D Read Write I/O Byte/Word Ready INTREQ INTACK BUS REQ BUS GRT ADDR & DATA BUS TIMING INTERRUPT DMA A D ADDR BUS DATA BUS (Bidirectional) MRD MWR INP OUT DONE I0I0 I1I1 InIn BUS REQ BUS GRT Addr Latch & Buffer Data Buf Control Logic & Buf Interrupt Priority Control Major Signal Groups: If time-multiplexed bus

RLH - Fall 1997RLH - Spring 1998ECE 611 Hardware - 8 Generic Memory Module Addr Decoder Buf Buf & Timing D D A A RD OE WR WE CS RAM ROM OE CS A D ADDR BUS DATA BUS MRD MWR Done (if async) A C (A-C) (Divides mem space) Draw mem map? RAM ROM (Data, Programs, Stack) (Bootstrap, OpSys, main program) modify R/W pulses Assert DONE after max RAM/ROM delay? Optional: DRAM & Controller Error Detect/Correct Multiple Banks

RLH - Spring 1998ECE 611 Hardware - 9 Generic I/O Module (1)

RLH - Spring 1998ECE 611 Hardware - 10 Generic I/O Module (2)

RLH - Spring 1998ECE 611 Hardware Microprocessor Interface Signals (1)

RLH - Spring 1998ECE 611 Hardware Microprocessor Interface Signals (2)

RLH - Spring 1998ECE 611 Hardware Microprocessor Interface Signals (3) l Memory-Mapped I/O Space l Lower-level Integration - must use custom designed “glue” part (PLDs?) Control Signals (which?) “Big Endian”

RLH - Spring 1998ECE 611 Hardware Micropocessor Interface Signals (1)

RLH - Spring 1998ECE 611 Hardware Micropocessor Interface Signals (2)

RLH - Spring 1998ECE 611 Hardware Micropocessor Interface Signals (3) l 2 Interface Configurations –Minimum Mode - small, single processor –Maximum Mode - large, multi-processor or coprocessor l Separate (port-mapped) I/O space l Highly integrated “glue” parts available “Little Endian”

RLH - Spring 1998ECE 611 Hardware Microcontroller l Complete, highly-integrated microcomputer –CPU, RAM, ROM, IO l Port 0 –8-bit bidirectional I/O port OR –multiplexed low-order address and data bus bytes l Port 1 –8-bit bidirectional I/O port l Port 2 –8-bit bidirectional I/O port OR –high-order address byte l Port 3 –8-bit bidirectional I/O port OR –various special-function signals

RLH - Spring 1998ECE 611 Hardware Microcontroller Interface Signals (1)

RLH - Spring 1998ECE 611 Hardware Microcontroller Interface Signals (2)

RLH - Spring 1998ECE 611 Hardware - 20 Basic Hardware Summary