Technical University Tallinn, ESTONIA DESIGN FOR TESTABILITY Raimund Ubar

Technical University Tallinn, ESTONIA Design for Testability Lectures Testability of Digital Systems Design for Testability Methods BIST/BISD Practical Works Two laboratory works Course work

Technical University Tallinn, ESTONIA Literature L.-T.Wang, C.-W.Wu, X.Wen. VLSI Test Principles and Architectures. Elsevier, 2006, 777 p. O.Novak, E.Gramatova, R.Ubar. Handbook of Testing Electronic Systems. Czech TU Publishing House, 2005, 395 p. A.Miczo. Digital Logic Testing and Simulation. Wiley-Interscience, New Yersey, 2003, 668 p. N.Jha, S.Gupta. Testing of Digital Systems. Cambridge Univ. Press, 2003, 1000 p. R.Ubar, J.Raik, Th.Vierhaus. IGI Global, Hershey – New York, 2011, 550 p.

Technical University Tallinn, ESTONIA Literature Other: H.-J.Wunderlich, Ed. Models in Hardware Testing. Springer, M.Gössel, E.Sogomonjan et. al. New Methods of Concurrent Checking. Springer, D.Gizopulos. Advances in Electronic Testing, Technology & Engineering. Springer, D.Gizopulos, A.Paschalis, Y.Zorian. Embedded Processor-Based Self-Test. Kluwer Acad. Publishers, 2004.

Technical University Tallinn, ESTONIA Goals of the DFT Course To give the basic knowledge: –How to improve test quality at increasing complexities of systems? This knowledges includes –understanding of how the physical defects can influence on the behavior of systems, and what is diagnostic modelling –understanding the meaning of testability, and how to design well testable systems –learning the basic methods of making systems self-testable The goal is also to give some hands-on experience of solving test related problems 5

Technical University Tallinn, ESTONIA Practical Importance of testability? To improve the manufacturing processes and to increase the yield To design reliable systems out of not reliable components which leads to the need of fault-tolerance Field diagnosis is the traditional task The Rule of Ten is the Sword of Damokles The increasing complexity of VLSI circuits has made test and diagnosis the most complicated problems in digital design 6 Automated diagnosis is needed

Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus © Raimund Ubar Why the topic of DFT is important? 7  Tiina Ubar 1.We depend too much on computers and on the technical systems controlled by computers

Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus © Raimund Ubar Computers and Embedded Systems Universal computers 2% Microprocessor market shares 98 % We notice our dependency on electronics only when it suddenly gives up to work 8 Embedded systems 98%

Research in ATI © Raimund Ubar Fault in the Patriot missile in the Gulf War - killing 28 soldiers and injuring 100 people Intel Pentium processor was found faulty - $475 millions of loss Ariane 5 reached the altitude of 3700 m and exploded – $7 billions of loss Space Shuttle Columbia disaster killing all 7 crew members Failure in the Toyota’s anti-lock brake system - 4,5 millions cars back to the industry Why the topic of DFT is important? 2. Engineering has two sides: -99% of the engireering creation brings us happiness -1% causes trouble (the blame against engineers) Engineering artifacts must be safe, secure and dependable In 5 years the US economic loss from computer bugs has increased 5 times Now 60 billions USD per year

Technical University Tallinn, ESTONIA Introduction: Testing World Test System Fault dictionary System model Test generation Fault simulation Test result Fault diagnosis Go/No go Located defect Test experiment Test tools (BIST)

© Raimund Ubar 11 What is a test? Test- program Test results Processor = ? 22 Diagnosis How many test patterns are needed to test an adder?

Technical University Tallinn, ESTONIA Hierarchy: Divide and Conquer The best place to start is with a good title. Then build a song around it. (Wisdom of country music) System 16 bit counter & 1 Sequence of 2 16 bits Sea of gates To generate a test for a component in a system, the computer needed 2 days and 2 nights An engineer did it „by hand“ with 15 minutes So, why computers? Engineer vs. computer: Design for Testability

Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus © Raimund Ubar Why the topic of DFT is important? The main property of today’s systems is COMPLEXITY To manage the complexity we have to know methods like: - abstraction - modeling - simulation - hierarchical „divide and conquer“ H.-J.Wunderlich, U Stuttgart

© Raimund Ubar 14 Why Design for Testability? Defect ? Expert systems were used in Europe but not in US Test generation process for detecting a fault: Expert system is needed to help the test programmer Know-how

© Raimund Ubar 15 Why Design for Testability? Hard-to-test- part Defekt ? New paradigm ScanPath Design Test generation process for detecting a fault: mindmappingsoftwareblog.com Gordion Knot

© Raimund Ubar 16 Alexander cuts the Gordian Knot Jean-Simon Berthélemy (1743–1811)

Technical University Tallinn, ESTONIA Making Systems Transparent Scan-Path design strategy Combinational circuit IN OUT R q q’ Combinational circuit IN OUT R Scan-IN Scan-OUT q q’ 17 theisleofwightcomputergeek.co.uk

Technical University Tallinn, ESTONIA Boundary Scan Standard

Technical University Tallinn, ESTONIA System under test Design for Testability Improving observability Improving controllability Control points To ways for improving testability with inserting of control points: 19

Technical University Tallinn, ESTONIA Introduction: Ad Hoc Design for Testability Method of Test Points: Block 1Block 2 Block 1 is not observable, Block 2 is not controllable Block 1Block 2 1- controllability: CP = 0 - normal working mode CP = 1 - controlling Block 2 with signal 1 1 CP Improving controllability and observability: OP Block 1Block 2 0- controllability: CP = 1 - normal working mode CP = 0 - controlling Block 2 with signal 0 & CP OP

Technical University Tallinn, ESTONIA Introduction: Tradeoffs Amusing testability: Theorem: You can test an arbitrary digital system by only 3 test patterns if you design it approprietly & & Solution: System  FSM  Scan-Path  CC  NAND & & & ? Proof:

Technical University Tallinn, ESTONIA Introduction: Built-in Self-Test Cores have to be tested on chip Source: Elcoteq Source: Intel 22 Copyright 2010 Raimund Ubar

Technical University Tallinn, ESTONIA Introduction: Self-Test in Digital Systems Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution –need for external ATE Combined solution –mostly on-chip, ATE needed for control On-chip solution –BIST

Technical University Tallinn, ESTONIA Self-Test in Complex Digital Systems 24 Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution –need for external ATE Combined solution –mostly on-chip, ATE needed for control On-chip solution –BIST

Technical University Tallinn, ESTONIA Introduction: What is BIST On circuit –Test pattern generation –Response verification Random pattern generation, very long tests Response compression IC

Technical University Tallinn, ESTONIA Introduction: SoC BIST Optimization: - testing time  - memory cost  - power consumption  - hardware cost  - test quality 

Technical University Tallinn, ESTONIA Course Work. Investigations of BIST Design of a circuit Evaluation of the testability of the circuit Redesign for testability –Control points selection, optimization –Scan path, optimization Built-in self-test. Design of solutions Experimental research

Technical University Tallinn, ESTONIA In-circuit –Test pattern generation –Response verification Pseudorandom test generation, very long tests Hybrid test solutions Response compression IC Course Work. Introduction

Technical University Tallinn, ESTONIA Course Work. Description of the Circuit 1. Design of a combinational circuit for the following functionality If x = 0, z = 0, then Y = k 1 A + k 2 B, else if x = 0, z = 1, then Y = k 3 A - k 1 C, else if x = 1, z = 0, then Y = (k 1 A  k 1 B  k 2 C)  (k 3 C  NOT (k 3 A)  k 1 B), else if x = 1, z = 1, then Y = k 4 A 2 + k 5 A + k 6 Coefficients k i can be found on the next slide

Technical University Tallinn, ESTONIA Vers. No. k1k1 k2k2 k3k3 k4k4 k5k5 k6k6 Vers no. k1k1 k2k2 k3k3 k4k4 k5k5 k6k ,10,20,581111,50,10, ,10,21,091101,50,11, ,10,22, ,50,42, ,10,23, ,50,43, ,11,00, ,50,80, ,11, ,50,81, ,12, ,5 2,0 Coefficients for the Course Work Versions

Technical University Tallinn, ESTONIA Course Work. Design of Interface Versions 2. Use three different interface versions for experiments: 1 bit, 2-bit and 4- or more bit interfaces for respective n-bit Signature Analyzers The types of interface:

Technical University Tallinn, ESTONIA Course Work. Design of a Testable Circuit 3.Enter the designed gate-level (AND, OR, NOT) combinational circuit into the computer, using CADENCE circuit editor 4.Generate test patterns with Turbo-Tester (TT) ATPG. If the fault coverage is 100%, remove one or more patterns from the test set, so that at least two faults remain undetected. 5.Improve the testability of the circuit to reach again 100% fault coverage with the updated test set Block 1Block 2 1- controllability: CP = 0 - normal working mode CP = 1 - controlling Block 2 with signal 1 1 CP OP

Technical University Tallinn, ESTONIA Course Work. Observability Investigation 6. Analyze two different testability improvement solutions: -Separate pins for all observability points -Single joint pin for all observability points Draw the graphics for both cases for the function P = f(T) where P is fault coverage, and T is test length 

Technical University Tallinn, ESTONIA Course Work. Design of a Test Generator 7. Generate test patterns by the BILBO tool for 10 different polynomials, and find the best structure for the LFSR Report for all 10 experiments the maximum achievable fault coverage, and fix the minimum test length needed for that Calculate the increase of the circuit size (in number of 2-input gates) due to adding of the self-test circuitry BILBO - Built- In Logic Block Observer: LFSR - Test Pattern Generator Combinational circuit LFSR - Signature analyzer

Technical University Tallinn, ESTONIA Course Work. Design of a Test Generator 8. Repeat the previous task for the case of using CSTP ("Circular Self Test Path") for self-test purposes CSTP - Circular Self-Test Path: LFSR - Test Pattern Generator & Signature analyser Combinational circuit

Technical University Tallinn, ESTONIA Course Work. Design of a Signature Analyzer 9. Carry out experiments with the best test set found in task 7 for 4 different Signature Analyzers: 1-bit, 2-bit, 4- bit, and 8-bit Calculate the fault coverages Draw the graphic P = f(SA), where P is the fault coverage and SA – is the number of bits in the Signature Analyzer Draw 4 graphics P = f(T), for 4 SA cases, where T – is the test length 5, 10, 15, 20 etc. up to P = 100% Explain the graphics 4 1) Y  1 bit SA 2) 2  2 bit SA Y 2  3) Y 4 n bit SA

Technical University Tallinn, ESTONIA Course Work. Store-and-Generate BIST Problem: low fault coverage The main motivations of using random patterns are: - low generation cost - high initial efeciency 0 2 n -1 Using many seeds: Pseudorandom test: Long PR test: Hard to test faults 0 2 n -1 Pseudorandom test:

Technical University Tallinn, ESTONIA Course Work. Store-and-Generate BIST 10. Synthesize an optimal BIST, using "store & generate“ architecture. Chose for that the best BILBO structure and ja the 100% test with length N. Minimize the number of seeds to be stored in the memory ROMTPGUUT ADR Counter 2Counter 1 RD CL 11. Compare the results in tasks 4, 5, 7, 8 and 10. Which solution is the best and why? Draw the block-level final structure of the selected best BIST solution. 12. Present a report of the course work.