Princess Sumaya Univ. Computer Engineering Dept. Review:
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 1 / 14 Digital Logic Review Objective Review a sample of MSI components and establish a standard drawing representation.
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 2 / 14 Digital Logic Review Logic Components Small Scale Integration (SSI) AND, OR, NOT … Medium Scale Integration (MSI) Multiplexer, Decoder, Register … Large Scale Integration (LSI) Microprocessor, Memory … Very Large Scale Integration (VLSI) Microprocessor, Memory …
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 3 / 14 Digital Logic Review Logic Circuits Combinational Output depends on the current input. Sequential Output depends on the current input and the previous output (history).
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 4 / 14 Digital Logic Review Logic Signals Values ●Totem–Pole (Binary): 0 or 1 ●Tri–State: 0, 1, or high–impedance ●Open–Collector: 0 or high–impedance Inversion (bubble)
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 5 / 14 Digital Logic Review Logic Signals Input ●0 or 1 Output ●0 or 1
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 6 / 14 Digital Logic Review Logic Signals Values ●Totem–Pole (Binary): Never leave inputs “open-circuit” Never “short circuit” outputs ●Tri–State: May connect multiple outputs but never enable more than one simultaneously ●Open–Collector: May connect multiple outputs Inactive value ?
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 7 / 14 Digital Logic Review Logic Signals Values ●Totem–Pole (Binary): ●Tri–State: ●Open–Collector: Use pull-up resistor
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 8 / 14 Digital Logic Review Signal Labels MUX MUXMUX I0I0 I1I1 I2I2 I3I3 Y S1S1 S0S0 Active High Signal Active Low Signal
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 9 / 14 Digital Logic Review Signal Labels Decoder DECODERDECODER E Y0Y0 Y1Y1 Y2Y2 Y3Y3 S1S1 S0S0
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 10 / 14 CLK Digital Logic Review Timing Diagram Clock Edge D Q ^ D Q ^ D Q ^ QAQA QBQB QCQC S CLK S QAQA QBQB QCQC S Last value Next value
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 11 / 14 Digital Logic Review Registers Group of “D” Flip – flops Single “Clock” Parallel “Load” REGISTERREGISTER D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLK LD
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 12 / 14 Digital Logic Review Registers Parallel “Load” MUX 0101 Y S D Q MUX 0101 Y S 0101 Y S 0101 Y S D Q D0 D1 D2 D3 Load CLK Q0 Q1 Q2 Q3
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 13 / 14 Digital Logic Review Buses CLK Bus23
Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 14 / 14 End of Review Digital Logic Review