Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM.

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Presentation transcript:

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Read-Write Memories (RAM)

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 6-transistor CMOS SRAM Cell

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM CMOS SRAM Analysis (Write)

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM CMOS SRAM Analysis (Read)

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 1-Transistor DRAM Cell

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM DRAM Cell Observations

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 1-T DRAM Cell

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Advanced 1T DRAM Cells Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer IsolationTransfer gate Storage electrode

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Periphery

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Dynamic Decoders

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 4 input pass-transistor based column decoder

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 4-to-1 tree based column decoder

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Sense Amplifiers

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Differential Sensing - SRAM

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Latch-Based Sense Amplifier

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Open bitline architecture

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM DRAM Read Process with Dummy Cell

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Open Bit-line Architecture —Cross Coupling

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Alpha-particles

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Yield Yield curves at different stages of process maturity (from [Veendrick92])

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Redundancy

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Redundancy and Error Correction