Lec 9Systems Architecture1 Systems Architecture Lecture 9: Assemblers, Linkers, and Loaders Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).

Lec 9Systems Architecture2 Introduction Objective: To review the MIPS instruction set and encoding. Objective: To learn how the MIPS assembler, linker, and loader work. Topics –Immediate instructions –Addressing in branches and jumps –Review MIPS instruction set and addressing modes –Instruction formats and encoding –Assembler –Linker and object files –Loader and executable files

Lec 9Systems Architecture3 MIPS Instruction Set Arithmetic/Logical –add, sub, and, or –addi, andi, ori Data Transfer –lw, lb –sw, sb –lui Control –beq, bne –slt, slti –j, jal, jr

1 May 2015Chapter 2 — Instructions: Language of the Computer 4 Assembler Pseudoinstructions Most assembler instructions represent machine instructions one-to-one Pseudoinstructions: figments of the assembler’s imagination move $t0, $t1 → add $t0, $zero, $t1 blt $t0, $t1, L → slt $at, $t0, $t1 bne $at, $zero, L –$at (register 1): assembler temporary

Lec 9Systems Architecture5 Small constants are used frequently (~50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18; Solution: use immediate format and hardwired registers –store / imbed constants in the low order 16-bits. –create hard-wired registers (like $zero) for constants. Design Principle: Make the common case fast. –Memory access can be x slower than accessing registers –Remove memory load delay / overhead –Store the constant in the instruction itself Immediate Addressing – Why?

Lec 9Systems Architecture6 MIPS Instruction Examples addi $29, $29, 4 slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4 I-Format machine code Example: addi $s0, $s0, 4 Immediate Addressing 816 4

Lec 9Systems Architecture7 How about larger constants? Since MIPS only allows 16-bit constants (a common case) Two instructions are required to imbed a 32-bit constant li $s0, 0x003c0900 will be translated by the assembler to –lui $s0, 0x003c; load upper immediate instruction –ori $s0, $s0, 0x0900 When constructing 32 bit offsets for memory addresses the MIPS assembler uses the $at register for temporary space $at stands for “assembler temporary” register

Lec 9Systems Architecture8 Loading a 32-bit Constant “load upper immediate instruction” lui places its 16-bit constant in the upper bit space lui $t0, Use ori (or immediate) to place the lower 15-0 bit space: ori $t0, $t0, lui ori result

Lec 9Systems Architecture9 Assembly provides convenient symbolic representation –“Mnemonics” are much easier than writing down numbers –Uniform feel to the instructions that hides machine code Machine language is the underlying reality –E.g., destination is no longer first –Difficult for human to use: time-consuming and error-prone Assembly can provide 'pseudoinstructions' –move, bgt, blt, etc. exist only in assembly code –Pseudoinstructions are translated to real instructions. When considering performance count the real instructions! Assembly Language vs. Machine Language

Lec 9Systems Architecture10 Simple instructions all 32 bits wide Well-organized and structured, no unnecessary baggage Only three instruction formats Overview of MIPS

Lec 9Systems Architecture11 Instructions: bne $t4,$t5,Label Next instruction is at Label if $t4≠$t5 beq $t4,$t5,Label Next instruction is at Label if $t4=$t5 I-Format : How to construct the branch target address: use PC+4 and add the (signed) value of immediate constant to it. This works because most branches are local, -- the target address is near by (principle of locality). Note: branches are restricted to 2 17 byte “distance” jumps. op rs rt 16 bit address I PC-relative Addressing in Branches

Lec 9Systems Architecture13 Pseudodirect Addressing in Jumps J-Format: Jump instructions use 28 high order bits of PC –Jumps are restricted to 2 28 byte jumps (256 MB) 32-bit address construction: –Take bits of PC+4 –Concatenate them to 26-bit constant (forms bits 27-2) –Append “00” to the “end” (bits 1-0) to reconstruct the byte address 6-bits 26-bit constant PC+4[31-28] 26-bit constant from j instruction

Lec 9Systems Architecture14 MIPS Encoding All instructions are 32-bits long Opcode is always in the high-order 6 bits Only three instruction formats 32 registers implies 5 bit register addresses: –$zero R0 ; zero register always equal to 0 –$at R1 ; temporary register (assembler temporary) –$v0 - $v1 R2-R3 ; return registers –$a0 - $a3 R4-R7 ; argument registers –$t0 - $t7 R8-R15 ; temporary - not preserved across calls –$s0 - $s7 R16-R23 ; saved registers - preserved across calls –$t8 - $t9 R24-R25 ; temporary not preserved across calls –$k0 - $k1 R26-R27 ; reserved by OS kernel –$gp R28 ; global pointer –$sp R29 ; stack pointer –$fp R30 ; frame pointer –$ra R31 ; return address

Lec 9Systems Architecture15 MIPS Addressing Modes Immediate Addressing –16 bit constant from low order bits of instruction –addi $t0, $s0, 4 Register Addressing –add $t0, $s0, $s1 Base Addressing (displacement addressing) –16-bit constant from low order bits of instruction plus base register –lw $t0, 16($sp) PC-Relative Addressing –(PC+4) + 16-bit address (word) from instruction –bne $s0, $s1, Target Pseudodirect Addressing –high order 4 bits of PC+4 concatenated with 26 bit word address - low order 26 bits from instruction shifted 2 bits to the left –j Address

Lec 9Systems Architecture16 Decoding Machine Code Example:

Lec 9Systems Architecture17 Design Principles Simplicity favors regularity –uniform instruction length –all ALU operations have 3 register operands –register addresses in the same location for all instruction formats Smaller is faster –register architecture –small number of registers Good design demands good compromises –fixed length instructions and only 16 bit constants –several instruction formats but consistent length Make common cases fast –immediate addressing –16 bit constants –only beq and bne

Lec 9Systems Architecture18 Translation Hierarchy

Lec 9Systems Architecture19 Assembler Translates assembly code to machine code Creates object file Symbolic labels to addresses Pseudoinstructions (move, la, li, blt, bgt,...) Assembly directives (.text,.globl,.space,.byte,.asciiz,...) Loading a 32-bit constant (lui and ori) Constructing 32-bit addresses (use $at) Branching far away (beq $s0, $s1, L1 => bne and j)

1 May 2015Chapter 2 — Instructions: Language of the Computer 20 Producing an Object Module Assembler (or compiler) translates program into machine instructions Provides information for building a complete program from the pieces –Header: described contents of object module –Text segment: translated instructions –Static data segment: data allocated for the life of the program –Relocation info: for contents that depend on absolute location of loaded program –Symbol table: global definitions and external refs –Debug info: for associating with source code

Lec 9Systems Architecture21 Format of Object File Object file header (size and position) Text segment (instructions - machine code) Data segment (data that comes with the program, both static and dynamic) Relocation information (instructions and data words that depend on absolute addresses when program is loaded into memory) Symbol table (external references) Debugging information

Lec 9Systems Architecture22 Linker Place code and data modules symbolically in memory Determine the addresses of data and instruction labels Patch both the internal and external references

1 May 2015Chapter 2 — Instructions: Language of the Computer 23 Linking Object Modules Produces an executable image 1.Merges segments 2.Resolve labels (determine their addresses) 3.Patch location-dependent and external refs Could leave location dependencies for fixing by a relocating loader –But with virtual memory, no need to do this –Program can be loaded into absolute location in virtual memory space

1 May 2015Chapter 2 — Instructions: Language of the Computer 24 Dynamic Linking Only link/load library procedure when it is called –Requires procedure code to be relocatable –Avoids image bloat caused by static linking of all (transitively) referenced libraries –Automatically picks up new library versions

1 May 2015Chapter 2 — Instructions: Language of the Computer 25 Lazy Linkage Indirection table Stub: Loads routine ID, Jump to linker/loader Linker/loader code Dynamically mapped code

Lec 9Systems Architecture26 MIPS Memory Convention

Lec 9Systems Architecture27 Loader Read executable file header to determine size of text and data segments Creates an address space large enough for the text and data Copies instructions and data from executable file into memory Copies parameters (if any) to the main program onto the stack Initializes the machine registers and sets stack pointer to first free location Jumps to a start-up routine that copies the parameters into the argument registers and calls the main routine of the program. When the main routine returns, the start-up routine terminates the program with an exit system call.

1 May 2015Chapter 2 — Instructions: Language of the Computer 28 Loading a Program Load from image file on disk into memory 1.Read header to determine segment sizes 2.Create virtual address space 3.Copy text and initialized data into memory Or set page table entries so they can be faulted in 4.Set up arguments on stack 5.Initialize registers (including $sp, $fp, $gp) 6.Jump to startup routine Copies arguments to $a0, … and calls main When main returns, do exit syscall

1 May 2015Chapter 2 — Instructions: Language of the Computer 29 Starting Java Applications Simple portable instruction set for the JVM Interprets bytecodes Compiles bytecodes of “hot” methods into native code for host machine

Lec 9Systems Architecture30 Linking Example

Lec 9Systems Architecture31 Resulting Executable File