Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

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Presentation transcript:

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area l Performance »Speed (delay) »Power Consumption »Energy

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter The Ideal Gate

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter VTC of Real Inverter

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter The CMOS Inverter: A First Glance

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS Properties l Full rail-to-rail swing l Symmetrical VTC l Propagation delay function of load capacitance and resistance of transistors l No static power dissipation l Direct path current during switching

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Voltage Transfer Characteristic

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter PMOS Load Lines V DSp I Dp V GSp =-5 V GSp =-2 V DSp I Dn V in =0 V in =3 V out I Dn V in =0 V in =3 V in = V DD +V+V GSp I Dn = - I Dp V out = V DD +V+V DSp V out I Dn V in = V DD -V GSp I Dn = - I Dp V out = V DD -V DSp

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS Inverter Load Characteristics in = 1 V in = 2 V in = 3 V in = 4 V in = 4 V in = 5 V in = 2 V in = 3

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS Inverter VTC

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Simulated VTC

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Gate Switching Threshold

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Impact of process variations

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter V IH, V IL and gain

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Propagation Delay

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Computing CMOS inverter delay in the quadratic model t V out V DD V dd - V TN

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter V DD V out V in = V DD R on C L t pHL = f(R on.C L ) = 0.69 R on C L t V out V DD R on C L ln(0.5) 0.36 Computing CMOS inverter delay in the linear model

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter NMOS/PMOS ratio

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Impact of Rise Time on Delay

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Delay as a function of V DD

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Power Consumption

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Where Does Power Go in CMOS? l Dynamic Power Consumption »Charging and Discharging Capacitors l Short Circuit Currents »Short Circuit Path between Supply Rails during Switching Leakage »Leaking diodes and transistors

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes!

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Short circuit current

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Minimizing SC Power Keep the input and output fall time the same

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Leakage (static) power Sub-threshold current is one of the most Compelling issues in low-energy design

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Reverse-biased diode leakage l J S =J S A l J S =1-5pA/µm 2 in 1.2µm CMOS l J S doubles with every 9 0 C in T

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter Sub-threshold leakage