1 BUFFERING APPROACH FOR ENERGY SAVING IN VIDEO SENSORS Wanghong Yuan, Klara Nahrstedt Department of Computer Science University of Illinois at Urbana-Champaign.

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1 BUFFERING APPROACH FOR ENERGY SAVING IN VIDEO SENSORS Wanghong Yuan, Klara Nahrstedt Department of Computer Science University of Illinois at Urbana-Champaign {wyuan1,

2 Motivation Video sensors become popular Processing Center Capture images Encode to frames Transmit to center Saving battery energy !

3 Opportunities Hardware level: performance vs. power – –Sleep, idle, active Switch into lower-power sleep – –Multiple frequencies/voltages (E  fV 2 ) Slow down to avoid idle Application level – –Encoding and transmission slack

4 Challenges Potentially – –Avoid CPU slack – –Sleep NIC when idle encoding transmission CPU NIC encoding transmission period However –Cannot avoid all slack Wait for transmission –NIC slack shorter than sleep cost (e.g., 40ms for WaveLAN)

5 Naïve Approach enc tran period f max slack CPU NIC slack One frame per period – –CPU: highest speed – –NIC: no sleep in slack Energy: period

6 DVS Approach CPU – –Slow down to shorten slack – –But, still some slack ! enc tran slow down f dvs CPU NIC enc f max Energy: Less !

7 Buffering Approach Why: Save both CPU and NIC energy – –Avoid all CPU slack – –Put idle NIC to sleep How: Buffering – –Encode one frame per period Timely, no data loss – –Buffer and send frames in bursts Accumulated slack > sleep cost

8 Buffering Approach CPU Energy: NIC Energy: Less !

9 Experiment Sender (HP Pavilion) Receiver (IBM ThinkPad) Athlon CPU DVS, implemented WaveLan Sleep, simulated H263 frames Speed: 300 – 1000MHz Power: 0.22 – 1 Watt Trans power: 1.5 W Idle power: 1 W Sleep power: 0.1 W Sleep cost: 40 ms

10 Results: Energy Save CPU energy by 32% - 83% Save NIC energy by 44%

11 Results: Delay Need to buffer only 1-3 frames

12 Conclusion Part of the Illinois GRACE project Cross-layer adaptation – –All layers are adaptive – –Cooperate For energy saving Application Operating System Network Protocols Architecture, Hardware Coordinator