Leveraging Software to Enhance Timing Analysis for Actel RTAX-S Devices Johnny Chung Corporate Applications Engineering Actel Corporation MAPLD 2005

2MAPLD 2005/1034Chung SmartTime  Achieve timing closure easier with Actel’s gate- level static timing analysis tool  fully integrated within Actel ’ s software solution  Enables complete timing analysis and timing constraints editing for RTAX-S designs to achieve desired performance  Ensure all timing constraints are met  Ensure design operates at the desired speed with the right amount of margin across all operating condition variations  Provides a selection of analysis types that enables the following:  Find the minimum cycle time that does not result in a timing violation  Identify paths with timing violations  Analyze delays of paths that have no timing constraints  Perform inter-clock domain timing verification  Perform maximum and minimum delay analysis for setup and hold checks  checks the timing requirements for violations while taking into account timing exceptions such as multicycle or false paths

3MAPLD 2005/1034Chung SmartTime  Timing Constraints Editor  You can add or modify timing constraints on a specific pin (for example, clock constraint) or on a specific set-of-paths (for example, maximum delay constraint) for your timing requirements and timing exceptions  User-friendly visual dialog boxes  Timing Analyzer  You can browse through the design’s various clock domains to examine the timing paths and identify those violating the timing requirements  You can also add or modify constraints for your timing requirements and timing exceptions

4MAPLD 2005/1034Chung SmartTime New Features  Provides a larger number of work-saving features compared to previous timing tool  External Setup/Hold  includes an external setup/hold domain browser to show the delay more clearly than previous timing tool  Input Delay Constraint  can be set according to External Setup/Hold constraint or as Input delay constraint  Visual constraint dialogs  Clock to Output Delay  SmartTime shows the entire path delay from the clock source through the clock pin of the register to the output port, an improvement over the previous timing tool

5MAPLD 2005/1034Chung SmartTime New Features  Provides a larger number of work-saving features compared to previous timing tool  Maximum Delay Constraint Priority  Maximum delay is seen as an exception to the clock constraint  Maximum delay constraint always has a higher priority than the clock constraint  Inter-Clock Domain  SmartTime allows the inter-clock domain analysis, an improvement over the previous timing tool  Flexibility in clock domain selection

6MAPLD 2005/1034Chung Setup Check in SmartTime to Aid RTAX-S Timing Analysis  Setup Check  Arrival time = Launch edge (0) + max Clock to FF1 + max Data path  Required time = Capture edge (T) + min Clock to FF2 – Setup of FF2  Slack = Required – Arrival = Violation if < 0

7MAPLD 2005/1034Chung Setup Check w/ Multicycle Paths for RTAX-S Timing Analysis  Add Multicycle Constraint  Fields are pre-filled with the path information

8MAPLD 2005/1034Chung Setup Check w/ Multicycle Paths for RTAX-S Timing Analysis  Setup Check  Arrival time = Launch edge (0) + max Clock to FF1 + max Data path  Required time = Capture edge (2T) + min Clock to FF2 – Setup of FF2  Slack = Required – Arrival = Violation if < 0

9MAPLD 2005/1034Chung Hold Check in SmartTime for RTAX-S Timing Analysis  Hold Check  Arrival time = Launch edge (0) + min Clock to FF1 + min Data path  Required time = Capture edge (0) + max Clock to FF2 + Hold of FF2  Slack = Arrival – Required = Violation if < 0

10MAPLD 2005/1034Chung Setup Check w/ Input Delay  Enter Constraint as Input Delay

11MAPLD 2005/1034Chung Setup Check w/ Input Delay  Enter Constraint as External Setup/Hold

12MAPLD 2005/1034Chung Setup Check w/ Input Delay in SmartTime for RTAX-S Timing Analysis  Setup Check  Arrival time = Launch edge (0) + max input delay + max Data path  Required time = Capture edge (T) + min Clock to FF1 – Setup of FF1  Slack = Required – Arrival = Violation if < 0

13MAPLD 2005/1034Chung Setup Check w/ Output Delay  Enter Constraint as Output Delay

14MAPLD 2005/1034Chung Setup Check w/ Output Delay  Enter Constraint as Clock-to-Out

15MAPLD 2005/1034Chung Setup Check w/ Output Delay in SmartTime for RTAX-S Timing Analysis  Setup Check  Arrival time = Launch edge (0) + max Data path  Required time = Capture edge (T) – Output Delay  Slack = Required – Arrival = Violation if < 0

16MAPLD 2005/1034Chung Inter-Clock Domains Timing Analysis  Larger designs may require interfacing between different clock domains  Designs with inter-clock domains requires timing verification between the related clocks  When functional paths exist across two clock domains, accurate specification of both clocks is required to allow a valid inter- clock domain timing check  This is important especially when the clocks are specified with different waveforms and frequencies  First step is to consider whether the inter-clock domain paths are false or functional  If functional, setup and hold check must be performed

17MAPLD 2005/1034Chung Inter-Clock Domains Timing Analysis  SmartTime timing analyzer for Actel RTAX-S FPGA timing analysis  SmartTime looks at the relationship between the active clock edges over a full repeating cycle, equal to the least common multiple of the two clock periods  The new common period represents a full repeating cycle (or pattern) of the two clock waveforms  For setup check, the tightest relation launch-capture is considered to ensure that the data arrives before the capture edge  The hold check verifies that a setup relationship is not overwritten by a following data launch Repeating cycle setup1 setup2

18MAPLD 2005/1034Chung Inter-Clock Domains in SmartTime

19MAPLD 2005/1034Chung Timing Report Options  Timing Report can be generated with different options, providing flexibility and customization for users  General setup  Filter report by slack threshold  Report using Maximum or Minimum delay analysis  Paths and Sets  Limit the number of paths to be reported in the timing report  Clock Domains  Limit reporting of clock domains to specific domains  More clear reporting format  Improvement over previous timing tool

20MAPLD 2005/1034Chung  Key enhancements from old timing report vs. new timing report  Old report format  New report format shows more detail for the specified path Timing Report Summary $Registers(Clock):$ClockPins() to $Registers(Clock):$InputPins Delay(ns) Slack(ns) Pins 9.17 N/A From: DFN1C1_Q_9_inst:CLK To: DFN1C1_Q_31_inst:D Set Register to Register From: DFN1C1_Q_9_inst:CLK To: DFN1C1_Q_31_inst:D Delay (ns): 9.17 Slack (ns): Arrival (ns): Required (ns): Setup (ns): Minimum Period (ns): 9.709

21MAPLD 2005/1034Chung Timing Report Summary (cont’d)  Additional details are available (expanded path) in the new timing report Clock Domain: Clock Expanded Path 1 From: DFN1C1_Q_9_inst:CLK To: DFN1C1_Q_31_inst:D data required time data arrival time slack ________________________________________________________ Data arrival time calculation Clock clock network DFN1C1_Q_9_inst:CLK (r) cell: ADLIB:DFN1C DFN1C1_Q_9_inst:Q (r) net: q_9_net_c XOR2_Sum_31_inst:Y (f) net: sum_31_net DFN1C1_Q_31_inst:D (f) data arrival time ________________________________________________________ Data required time calculation Clock clock network DFN1C1_Q_31_inst:CLK (r) Library setup: ADLIB:DFN1C DFN1C1_Q_31_inst:D data required time