CM-5 Massively Parallel Supercomputer ALAN MOSER Thinking Machines Corporation 1993

CM-5 General Information Brain child of Brain child of W. Daniel Hillis W. Daniel Hillis Lewis W. Tucker Lewis W. Tucker Founded Thinking Machines Corporation in the 1980’s CM-5 was last in a line of successors to the original CM-1 Connection Machine

CM-5 Connection Machine Hardware Overview processing nodes each of which contain a 32 MHz SPARC RISC processor 32 MB of distributed memory although the size may vary according to customer specifications 128 Mflops (per processing node) yielding a total performance of 1Teraflops. Tera=2^40 or roughly 10^12

Processing Node vs. Processor Processing Node not a single processor but a set of 5 chips Single 32 MHz SPARC RISC processor with 4 separate vector units capable of performing 64 bit floating point and integer arithmetic

Diagram of Processing Node

CM-5 Operating System CM-5 runs the CMOST OS enhanced version of the UNIX OS Each processing node contains a microkernal of the OS

CM-5 MIMD or SIMD Machine? Referred to as synchronized MIMD machine somewhere between MIMD and SIMD best aspects of both types of machines

CM-5 Batch Processing or Timesharing? CM-5 allows both Batch processing and Timesharing Timesharing is provided by dividing processing nodes into a partition controlled by partition manager Protection is enforced by hardware so that one partition cannot interfere with another

Interconnection Network(s) What? CM-5 has not one but three overlapping interconnection networks Data Network Control Network Diagnostic Network

3 Overlapping Interconnection Networks

CM-5 Data Network Supports simultaneous sending of messages between processing nodes Solves several problems: balancing message loads in network “fetch-deadlock problem” timesharing a parallel computer

CM-5 Data Network Binary fat tree

CM-5 Data Network (cont.) Messages are passed between processing nodes using the least common ancestor Increasing bandwidth at each level up Avoids “bottlenecks” at the root node

CM-5 Control Network Designed a simple tree Provides synchronization so as to allow CM-5 to operate like SIMD computer In general control network provides for: fast broadcasting of data barrier synchronization parallel prefix/postfix scan operations

CM-5 Diagnostic Network Organized as incomplete binary tree Able to map-out or ignore parts of the tree that are faulty Able to select and access groups of system chips in parallel including: single chip single type of chip chips within a user partition chips associated within portion of the system such as board, cabinet, etc.

CM-5 Diagnostic Network Diagram

References “The Network Architecture of the Connection Machine CM-5”, Thinking Machines Corporation February 7, 1996 Hillis, Daniel and Tucker, Lewis “The CM-5 Connection Machine: A Scalable Supercomputer” Communications of the ACM, November 1993 Volume 36, Number 11