Shift Register Application Chapter 22 Subject: Digital System Year: 2009.

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Presentation transcript:

Shift Register Application Chapter 22 Subject: Digital System Year: 2009

Overview Time Delay Serial to Parallel Data Converter UART

Time Delay The serial in/serial out shift register can be used to provide a time delay from input to output that is a function of both the number of stages (n) in the register and the clock frequency. Bina Nusantara University 4

Shift Register as a time delay device Bina Nusantara University 5 When a data pulse is applied to the serial input as shown Below (A and B connected together), it enters the first stage on the triggering edge of the clock pulse. It is then shifted from stage to stage on each successive clock pulse until it appears on the serial output n clock periods later.

Serial-to-Parallel Data Converter Serial data transmission from one digital system to another is commonly used to reduce the number of wires in the transmission line. For example, eight bits can be sent serially over one wire, but it takes eight wires to send the same data in parallel. Bina Nusantara University 6

Serial-to-Parallel Data Converter Bina Nusantara University 7

Serial-to-Parallel Data Converter Bina Nusantara University 8

Universal Asynchronous Receiver Transmitter (UART) Bina Nusantara University 9 computers and microprocessor-based systems often send and receive data in a parallel format. Frequently, these systems must communicate with external devices that send and/or receive serial data. An interfacing device used to accomplish these conversions is the UART (Universal Asynchronous Receiver Transmitter).

UART Interface Bina Nusantara University 10

Basic UART Block Diagram Bina Nusantara University 11