Carbon nanotube field effect transistors (CNT-FETs) have displayed exceptional electrical properties superior to the traditional MOSFET. Most of these fabrication methods for CNT electronic devices are based on either random positioning or directed assembly by high temperature growth on patterned substrate, which are not compatible with conventional CMOS technologies. Most of these devices are controlled by only a global back gate. They do not offer high throughput or individual control of each CNT-FET necessary for parallel fabrication. For large-scale fabrication of CNT-FET devices three conditions need to be satisfied: (i) separation of semiconducting and metallic carbon nanotubes must be realized, (ii) nanotubes need to be assembled at selected positions of the circuit with high yield, and (iii) each nanotube must be addressed individually with a local gate. We present a simple and scalable technique for the fabrication of CMOS compatible and local gated CNT-FETs from solution. The approach is based on directed assembly of individual SWNT via AC Dielectrophoresis. CONCLUSION We have fabricated CNT-FETs with local Al bottom gates through DEP. Our method offers a convenient way to assemble local-gated CNT-FET devices from solution without the need of high temperature growth, making it compatible with present microfabrication technology. Our local-gated devices show superior characteristics such as small values of threshold swing and low threshold voltage compared to other DEP assembled back gated CNT- FETs. Local gating offers fast switching behavior due to the channel controlled mechanism owed to the thin local Al gate. Directed assembly of local gated CNT-FETs at selected position of the circuit via DEP may pave the way for large scale fabrication of CMOS compatible nanoelectronic devices. Figure 3: Drain current (I DS ) - back gate voltage (V BG ) characteristics of representative DEP assembled metallic (a) and semiconducting (b) devices (V DS = 0.3 V). 1. Electronic Transport Characteristics of DEP Assembled Device 1.Tans et al., Nature, 393, 49 (1998). 2.Kasper Grove-Rasmussen, University of Copenhage, Denmark, PhD thesis (2006). 3.Dong et al, J. Phys. Chem. B (2005). 4.Lin et al, IEEE Elec. Dev. Lett (2005). 5.Javey et al, Nature Mater (2002). 6.P. Stokes and S. I. Khondaker, Nanotechnology (2008). Figure 2: Fabrication of local gated CNT-FET device. (a) Source (S) - drain (D) electrodes of 1 μm separation are patterned. (b) Local Al/Al gate electrodes are patterned using EBL. (c) DEP assembly of CNT from solution. (d) AFM image of a device showing nanotubes are assembled at the tips. Devices were fabricated on heavily doped silicon (Si) substrates capped with a thermally grown 250 nm thick SiO 2 layer. Contact pads and electron beam markers were fabricated with optical lithography using double layer resists, metallization of Cr (5 nm) and Au (50 nm) and finally standard lift-off. Source and drain electrode patterns were defined with EBL 5 nm Cr and 20 nm thick Au were thermally deposited followed by lift-off. 100 nm wide Al gate patterns are defined by EBL with nm thickness. The sample is treated in oxygen plasma to create a thin aluminum oxide dielectric layer. DEP assembly: HiPco grown SWNTs (Carbon Nanotechnologies Inc.) was ultrasonically dispersed in 5 ml of 1,2-dichloroethane for approximately 30 minutes. A small drop (~8ul) was cast onto a chip with 12 pairs of source-drain electrodes, each containing a 100 nm wide Al gate. An AC voltage of approximately 8 V P-P at 1 MHz is applied for 1-2 seconds. METHODS RESULTS REFERENCES INTRODUCTION & MOTIVATION Figure 6: (a) Electric field simulation between a 1 um gap. Shows that the gradient of electric field is strongest near the tips of the electrodes. (b) Plot of the Clausius Mosetti factor (K F ) for SWNTs in dichloroethane. The force is positive for both semiconducting and metallic SWNTs up to ~5 GHz. Figure 5: (a) I DS versus V LG and V BG for comparison form the same device after DEP assembly. Local gate shows far better gate coupling. INSET: Expanded plot of I DS vs. V LG showing low threshold voltage and subthreshold swing. The gate leakage current is < 1 pA. (fast switching is possibly due to channel controlled operation). b) Output characteristics, for different gate voltages up to the saturation regime. 2. Electrical Breakdown of Metallic SWNT Device Fabrication and Dielectrophoretic Assembly Figure 1: (a) Random placement of CNT by drop casting from solution. (b) Patterned growth from CVD. Requires temperatures of 900 C. b) Local Gate Back Gate Si SiO 2 Au 200nm D S LG SWNT Si back gate SiO 2 Au 1MHz, 8V p-p HiPCO SWNTs Local-Gated Single-Walled Carbon Nanotube Field Effect Transistors Assembled by AC Dielectrophoresis Paul Stokes and Saiful I. Khondaker Nanoscience Technology Center and Department of Physics, University of Central Florida, Florida 32826, USA 3. Local Gate Characteristics 5. Electric Field Simulation After Electrical Breakdown Figure 4: (a) Transformation of a nanotube bundle into a semiconducting device by selective breakdown by sequential ramps of V DS (labeled 1 and 2) with back gate set to 10 V. INSET: Resultant current - back gate characteristic after breakdown (V DS = 0.3 V). Au SiO 2 Al 2 O 3 4. Comparison to Other DEP and CVD Assembled CNT-FETs (a) (b) 50% Metallic (a) 50% Semiconducting (b) (a) (b) (a) (b) (a) (b ) (a) (b) (c) (d) Catalytic Island Al/Al 2 O 3 local gate