Crystal Inc. CS8900A-ISA Ethernet Controller Presented by Kallol Par April,

Key Features ► Low Cost  4K Integrated RAM  On-chip 10Base-T filters (so no filter/transformer packages)  Designed to fit on 2-layer circuit board  Small PCB footprint - Thin Quad Flat Pack ► High Performance  Software selectable I/O, Memory mode for optimum performance through PacketPage™ Architecture  Early interrupts allow the host to preprocess incoming frames

Key Features ► Low Power modes  Hardware Standby ► Chip powered down, only 10Base-T receiver enabled for Link Activity  Software Standby / Suspend ► Receiver is also disabled ► Current consumption in micro-amperes

Pin description ► ISA Bus interface  SA[0:19] – system address bus  SD[0:15] – system data bus  RESET – Active high to reset  AEN – For DMA operations  MEMR/MEMW – value indicating Read/Write operation from host  IOR/IOW – value indicating I/O Read/Write operation from host  INTRQ[0:3] – Active-high indicates interrupt presence ► EEPROM Interface  EEDI/EEDO – EEPROM data I/O pins ► 10 Base-T interface  TxD+ / TxD- - Differential output pair 10Mb/s Manchester-encoded data  RxD+ / RxD- - Differential input pair 10Mb/s Manchester-encoded data ► General Pins  XTAL[1:2] – 20 Mhz crystal input  LINKLED – Controlled by software to be alternatively used as a Link pulse indicator  LANLED – Indicates packet reception  AVDD, AVSS – 3.3V, ground reference

Functional Block Diagram

PacketPage Architecture ► 4 K-byte of integrated RAM ► Highly efficient means of accessing internal registers and buffer memory ► Used for temporary storage of transmit and receive frames ► Direct access in Memory mode ► Indirect access in I/O mode

► User-accessible portion of PacketPage is divided in six sections 1. Bus Interface Registers (PacketPage base h..0045h) Used to configure the CS8900A’s ISA-bus interface and map the CS8900A into the host system’s I/O and Memory space

Section 2 Status and Control Registers (0100h – 013Fh)  Control how frames will be transmitted and received

Status and Control Registers (0100h – 013Fh).. Contd.

Section 3 Initiate Transmit Registers TxCMD, TxLength (0144h – 0146h) Section 4 Address filter Registers – Logical address, Individual Address (0150h – 0158h) Section 5 Receive Frame location – RxStatus, RxLength, Receive frame length (0400h – 0404h) Section 6 Transmit Frame location (0A00)

PacketPage Architecture ► Memory mode  Directly access the PacketPage registers by mapping PacketPage on a 4K boundary on the host  Controlled through MEMR/MEMW pins  Faster than I/O mode ► I/O mode  Default mode of operation  PacketPage registers are accessed through PacketPointer location and Packet Data port  Controlled through IOR/IOW pins  The I/O mode mapping is as follows: ► 0000h - Receive/Transmit data (Port 0) ► 0002h – Receive/Transmit data (Port 1) ► 0004h – TxCMD ► 0006h – TxLength ► 0008h – Interrupt Status Queue ► 000Ah – PacketPage pointer  Store the register address here ► 000Ch – PacketPage data (Port 0)  Store the actual register data here (16 bits) ► 000Eh – PacketPage data (Port 1)

Ethernet interface – Functional Description ► IEEE Ethernet standard

MAC Frame Encapsulation ► Generate the Preamble, SFD and FCS for user data ► Transmission Error Detection and Handling  Can be configured to interrupt host  Controlled through registers – TxEvent, TxCFG  Transmit Collision interrupt generated after 16 frame collisions

MAC Frame Reception ► If SFD present, valid frame data next ► If (DA = Self MAC address), copy frame into CS8900A buffer memory ► Reception Error Detection and Handling  Can be configured to interrupt host  Controlled through registers – RxEvent, RxCFG  CRC Error, Runt frame ( 1518)

MAC Management ► Collision Avoidance  Two-part deferral ► No internal carrier sense activates the Inter-Packet Gap (IPG) timer for 9.6 micro seconds  Simple Deferral ► Waits for the entire 9.6 micro seconds ► Collision Resolution  Normal Collision ► First 512 bytes  Late Collision ► After 512 bytes  Jam sequence  Back-off algorithm ► 0 <= r <= 2^k

Encoder/Decoder (ENDEC)

► Manchester encoding of NRZ MAC data  Transmit clock generated through 20 Mhz quartz crystal ► Carrier detection  Carrier sense asserted during packet reception (and also during any network activity), and de-asserted after EOF is received ► Recovering NRZ data from Manchester-encoded data  PLL restarts on Carrier sense and locks on incoming data  Phase difference is removed before conversion to NRZ

10Base-T Transceiver

► 10 Base-T filters  Low pass filters eliminate need for external filters ► Transmitter  Wave shaping on Manchester-encoded data from ENDEC ► Receiver  Squelch circuit to validate signal amplitude

Ethernet Packet Format

Basic Frame Reception

Basic Frame Pre-processing

Early Interrupt generation

Basic Frame Transmission

Basic Frame Transmission – Interrupt driven

Reference The CS8900A data sheet