Software Defined Radio Lec 7 – Digital Generation of Signals Sajjad Hussain, MCS-NUST.

Outline for Today’s Lecture Digital Generation of Signals 1. Introduction 2. Comparison to Analog generation 3. DDS Techniques 4. Analysis of Spurious Contents 5. Band-pass Signal Generation 6. Performance of DDS Systems 7. Generation of Random Numbers 8. ROM compression techniques

Generation of Random Sequences Random sequences are needed in a variety of communication applications  scrambling, bit- synchronization, spreading, security etc. Spreading  Use of different codes for same freq. Scrambling  Help maintain synchronization and adding randomness.. Ideal binary random sequence (infinite length, identically distributed RV ) vs. PN sequences (finite length)

Type of Sequences Most common technique for generating PN sequences  use of binary digital linear feedback shift register Maximum Length Sequences  Sequences with a maximum-period are called max length seq.  m- sequences  Shift register with 2 m -1 period -> polynomial should be primitive-> irreducible-> cannot be factored into product of polynomials with binary coefficients and degrees of at-least 1 If N = 2 m -1 is the period of sequence y(n), then the periodic auto-correlation function is

Gold Sequences Composite codes with good and well-defined cross-correlation properties Generated by using ‘preferred m-sequences’  m-sequences with certain specific correlation properties  Modulo-2 sum of 2 preferred m-sequences  Same length as that of input codes  A different code is generated by shifting one of the codes  Thus construction of 2 m -1 codes from pairs of m-stage shift registers Though constructed from m-sequences, are not maximal sequences Codes can be selected with bounded cross-correlation properties

Gold Code Generator

Gold Codes with bounded auto- correlation

Randomization with Wheatley procedure Used for removal of harmonic spurs If removal not possible, spreading energy in all harmonics is useful – Wheatley procedure  high noise floor with few strong harmonics Randomly varying (dithering) the periods of output, while keeping the average of these periods unchanged The method consists of adding a sequence of random numbers to the contents of the accumulator in a prescribed manner to convert harmonic signals into a continuous noise floor, whose level is much lower than that of harmonic signals At each clock-cycle a RV is added – 0:Δ r -1  Introduces un-correlated phase noise

Wheatley Procedure

Effect on Spectrum because of Wheatley Procedure

ROM Compression Spurious signals are one of the main drawbacks of DDS system, especially those caused by phase- truncation – spurious harmonic signals phase-truncation – to avoid a very large ROM Phase-truncation can be avoided if it was possible to compress more information into the ROM One simple compression approach takes advantage of the symmetry of sine-wave  store only one quadrant of information  eliminates 75% of the normal memory requirements Other techniques along-with the sine-symmetry – interpolation-based

Interpolation using Taylor Series Expansion Certain values of sine function are stored in ROM and the values in-between these angles can be interpolated using Taylor series expansion

Interpolation using two terms of power series

Effect of using four-terms of power series

Effect of using seven-terms of power series

Interpolation using trignometric identities Using trigonometric identities to find the values between the exact known values  Most of these methods work only well when the deviation from the known angle is very small Hutchison Algorithm :  Division of values of sine function in first quadrant into ‘coarse’ and ‘fine’ ROM  Trig. Identities can then be used to generate the sine values for any angle θ by decomposing it to values contained in the coarse and fine ROM  No. of bits addressing the ROM are divided into C coarse bits (for θ C ) and F fine bits (for θ F )  If θ= θ C + θ F

Example : ROM size savings using Hutchison algorithm For an accumulator (address) width = 12 bits and ROM width = na = 12 bits  total no. of bits stored is 2 12 * 12 = 49,152 Same resolution can be obtained using a lesser no. of stored bits by Hutchison algorithm If C= 8 bits and F = 4 bits Total no. of bits required for storing  2 4 * * 12 = 3,264 bits

Sunderland algorithm An improvement over Hutchison algorithm and divides the phase-angle into three parts, thus using 3 ROMs  θ= θ C + θ s + θ F The coarse angles are defined in the first quadrant of a sine-wave from 0 to π/2, divided into 2 C equal angles. The Sunderland angle is defined as one of coarse angles divided into 2 S equal angles. Finally, the fine angle is defined as one of the Sunderland angles divided into 2 F equal angles

Sine-Phase Difference Algorithm Approach Introduces a way to reduce the storage requirements for the quarter-wave sine function. The idea is to store f(θ) = sin (πθ/2) – θ, instead of sin (πθ/2) The variation in the function f(θ) values is small, and thus a small LUT (as many as two bits saving for storing amplitude values) can be used to represent f(θ) and sin (πθ/2) can be easily calculated from f(θ) Sine LUT propagation delay is also reduced, increasing the maximum clock freq. of DDS

Modified Sine-Phase Difference Algorithm Approach – Parabolic Approximations In this approach, a parabola is used to approximate the sinusoid of the sine half-period To generate the same sine wave, the sine parabola difference approximation uses a more narrow range of values (saves as many as 4 bits of memory word-length) than the sine-phase difference approach Additional hardware to generate corresponding parabola values at ROM output can be easily implemented without significant complexity

Example : Qualcomm’s Q2240 Direct Digital Synthesizer Suited for needs of wireless comm. And complex waveform synthesis Max freq. 100 MHz (5V) or 60 MHz (3.3 V) 31-bit Freq. Control Register (FCR), 32-bit phase-accumulator, 14– bit address output and 12-bit sine LUT  14-bit phase output resolution  12-bit output resolution The latched FCR value is accumulated in the phase-accumulator in every clock-cycle The LUT can be by-passed, ending the 14 MSBs of the phase- accumulator directly to the output The unused sine LUT is de-activated to reduce power consumption

Block Diagram of Qualcomm’s DDS – Q2240I-3S1

Conclusion DDS in comparison to analog approaches provide  Flexibility  Fine freq. resolution  Fast response time  Ease-of-manufacturing and testing  Robustness to environmental changes Most DDS  ACC + ROM + DAC Issue in DDS Design  Spurious signal removal  Hybrid designs  ROM-size constraints  compression techs., trig. Identities. Etc.