Transmission Line Network For Multi-GHz Clock Distribution Hongyu Chen and Chung-Kuan Cheng Department of Computer Science and Engineering, University.

Slides:



Advertisements
Similar presentations
EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department.
Advertisements

Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.
Chapter 7 Operational-Amplifier and its Applications
4/22/ Clock Network Synthesis Prof. Shiyan Hu Office: EREC 731.
FPGA Latency Optimization Using System-level Transformations and DFG Restructuring Daniel Gomez-Prado, Maciej Ciesielski, and Russell Tessier Department.
1/42 Changkun Park Title Dual mode RF CMOS Power Amplifier with transformer for polar transmitters March. 26, 2007 Changkun Park Wave Embedded Integrated.
Fundamentals of Electric Circuits Chapter 10 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
CSE245: Computer-Aided Circuit Simulation and Verification Lecture Note 2: State Equations Prof. Chung-Kuan Cheng 1.
Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient inductance model RC and RLC circuit model generation.
Lecture 8: Clock Distribution, PLL & DLL
Clock Distribution Scheme using Coplanar Transmission Lines Victor Cordero Sunil P Khatri Department of ECE Texas A&M University
1 Interconnect and Packaging Lecture 7: Distortionless Communication Chung-Kuan Cheng UC San Diego.
Interconnect and Packaging Lecture 2: Scalability
1 A Single-supply True Voltage Level Shifter Rajesh Garg Gagandeep Mallarapu Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M.
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu (Kevin) Cao 1, Chenming Hu 1, Xuejue Huang 1, Andrew.
UCSD CSE245 Notes -- Spring 2006 CSE245: Computer-Aided Circuit Simulation and Verification Lecture Notes Spring 2006 Prof. Chung-Kuan Cheng.
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield A. B. Kahng, B. Liu, X. Xu, J. Hu* and G. Venkataraman*
Statistical Gate Delay Calculation with Crosstalk Alignment Consideration Andrew B. Kahng, Bao Liu, Xu Xu UC San Diego
1 Enhancing Performance of Iterative Heuristics for VLSI Netlist Partitioning Dr. Sadiq M. Sait Dr. Aiman El-Maleh Mr. Raslan Al Abaji. Computer Engineering.
RLC Interconnect Modeling and Design Students: Jinjun Xiong, Jun Chen Advisor: Lei He Electrical Engineering Department Design Automation Group (
THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis.
Noise and Delay Uncertainty Studies for Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu † and Devendra Vidhani ‡ UCLA Computer Science Department,
More Realistic Power Grid Verification Based on Hierarchical Current and Power constraints 2 Chung-Kuan Cheng, 2 Peng Du, 2 Andrew B. Kahng, 1 Grantham.
Worst-Case Timing Jitter and Amplitude Noise in Differential Signaling Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, and Yu Hu Electrical Engineering Dept.,
Javad Lavaei Department of Electrical Engineering Columbia University Joint work with Somayeh Sojoudi Convexification of Optimal Power Flow Problem by.
Announcements Assignment 3 due now, or by tomorrow 5pm in my mailbox Assignment 4 posted, due next week –Thursday in class, or Friday 5pm in my mailbox.
A Methodology for Interconnect Dimension Determination By: Jeff Cobb Rajesh Garg Sunil P Khatri Department of Electrical and Computer Engineering, Texas.
Logic Optimization Mohammad Sharifkhani. Reading Textbook II, Chapters 5 and 6 (parts related to power and speed.) Following Papers: –Nose, Sakurai, 2000.
CSE245: Computer-Aided Circuit Simulation and Verification Lecture Note 2: State Equations Prof. Chung-Kuan Cheng.
© H. Heck 2008Section 2.41 Module 2:Transmission Lines Topic 4: Parasitic Discontinuities OGI EE564 Howard Heck.
Introduction to Adaptive Digital Filters Algorithms
ENE 428 Microwave Engineering
EKT 441 MICROWAVE COMMUNICATIONS
In Engineering --- Designing a Pneumatic Pump Introduction System characterization Model development –Models 1, 2, 3, 4, 5 & 6 Model analysis –Time domain.
1 Numerical and Analytical models for various effects in models for various effects inEDFAs Inna Nusinsky-Shmuilov Supervisor:Prof. Amos Hardy TEL AVIV.
ECE 546 – Jose Schutt-Aine 1 ECE 546 Lecture -04 Transmission Lines Spring 2014 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois.
Research on Analysis and Physical Synthesis Chung-Kuan Cheng CSE Department UC San Diego
An Efficient Algorithm for Dual-Voltage Design Without Need for Level-Conversion SSST 2012 Mridula Allani Intel Corporation, Austin, TX (Formerly.
1 Interconnect and Packaging Lecture 8: Clock Meshes and Shunts Chung-Kuan Cheng UC San Diego.
1 Passive Distortion Compensation for Package Level Interconnect Chung-Kuan Cheng UC San Diego Dongsheng Ma & Janet Wang Univ. of Arizona.
Integrated Placement and Skew Optimization for Rotary Clocking A paper by: Ganesh Venkataraman, Student Member, IEEE, Jiang Hu, Member, IEEE, and Frank.
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation Keng-Jan Hsiao and Tai-Cheng Lee National Taiwan University Taipei, Taiwan.
Synchronization in complex network topologies
1 Passive Distortion Compensation for Package Level Interconnect Chung-Kuan Cheng UC San Diego Dongsheng Ma & Janet Wang Univ. of Arizona.
Fundamentals of Electric Circuits Chapter 10 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
1 Interconnect/Via. 2 Delay of Devices and Interconnect.
Distributed Computation: Circuit Simulation CK Cheng UC San Diego
Introduction to Clock Tree Synthesis
CSE245: Computer-Aided Circuit Simulation and Verification Lecture Note 2: State Equations Spring 2010 Prof. Chung-Kuan Cheng.
19.4 Load-dependent properties of resonant converters
Surfliner: Distortion-less Electrical Signaling for Speed of Light On- chip Communication Hongyu Chen, Rui Shi, Chung-Kuan Cheng Computer Science and Engineering.
1ISPD'03 Process Variation Aware Clock Tree Routing Bing Lu Cadence Jiang Hu Texas A&M Univ Gary Ellis IBM Corp Haihua Su IBM Corp.
Low-Power and High-Speed Interconnect Using Serial Passive Compensation Chun-Chen Liu and Chung-Kuan Cheng Computer Science and Engineering Dept. University.
High Performance Interconnect and Packaging Chung-Kuan Cheng CSE Department UC San Diego
1 Revamping Electronic Design Process to Embrace Interconnect Dominance Chung-Kuan Cheng CSE Department UC San Diego La Jolla, CA
1 Timing Closure and the constant delay paradigm Problem: (timing closure problem) It has been difficult to get a circuit that meets delay requirements.
1 Modeling and Optimization of VLSI Interconnect Lecture 2: Interconnect Delay Modeling Avinoam Kolodny Konstantin Moiseev.
Managed by UT-Battelle for the Department of Energy Vector Control Algorithm for Efficient Fan-out RF Power Distribution Yoon W. Kang SNS/ORNL Fifth CW.
Lab2: Smith Chart And Matching
Cristian Ferent and Alex Doboli
Ali Fard M¨alardalen University, Dept
High Performance Interconnect and Packaging
EE201C Chapter 3 Interconnect RLC Modeling
topics Basic Transmission Line Equations
Circuit Design Techniques for Low Power DSPs
Simon Lineykin and Sam Ben-Yaakov*
Wire Indctance Consequences of on-chip inductance include:
Reducing Total Network Power Consumption
ELECTRONICS II 3rd SEMESTER ELECTRICAL
Interconnect and Packaging Lecture 2: Scalability
Presentation transcript:

Transmission Line Network For Multi-GHz Clock Distribution Hongyu Chen and Chung-Kuan Cheng Department of Computer Science and Engineering, University of California, San Diego January 2005

Outline Introduction Problem formulation Skew reduction effect of transmission line shunts Optimal sizing of multilevel network Experimental results

Motivation Clock skew caused by parameter variations consumes increasingly portion of clock period in high speed circuits RC shunt effect diminishes in multiple- GHz range Transmission line can lock the periodical signals Difficult to analysis and synthesis network with explicit non-linear feedback path

Related Work (I) I. Galton, D. A. Towne, J. J. Rosenberg, and H. T. Jensen, “Clock Distribution Using Coupled Oscillators,” in Prof. of ISCAS 1996, vol. 3, pp Transmission line shunts with less than quarter wavelength long can lock the RC oscillators both in phase and magnitude

Related work (II) V. Gutnik and A. P. Chandraksan, “Active GHz Clock Network Using Distributed PLLs,” in IEEE Journal of Solid-State Circuits, pp , vol. 35, No. 11, Nov Active feedback path using distributed PLLs Provable stability under certain conditions

Related work (III) F. O’Mahony, C. P. Yue, M. A. Horowitz, and S. S. Wong, “Design of a 10GHz Clock Distribution Network Using Coupled Standing-Wave Oscillators,” in Proc. of DAC, pp , June 2003 Combined clock generation and distribution using standing wave oscillator Placing lamped transconductors along the wires to compensate wire loss

Related work (IV) J. Wood, et al., “Rotary Traveling-Wave Oscillator Arrays: A New Clock Technology” in IEEE JSSC, pp , Nov Clock signals generated by traveling waves The inverter pairs compensate the resistive loss and ensure square waveform

Our contributions Theoretical study of the transmission line shunt behavior, derive analytical skew equation Propose multi-level spiral network for multi-GHz clock distribution Convex programming technique to optimize proposed multi-level network. The optimized network achieves below 4ps skew for 10GHz rate

Problem Formulation Inductance diminishes shunt effect Transmission line shunts with proper tailored length can reduce skew Differential sine waves Variation model Hybrid h-tree and shunt network Problem statement

Inductance Diminishes Shunt Effects f(GHz) skew(ps) um wide 1.2 cm long copper wire Input skew 20ps

Wavelength Long Transmission Line Synchronizes Two Sources

Differential Sine Waves Sine wave form simplifies the analysis of resonance phenomena of the transmission line Differential signals improve the predictability of inductance value Can convert the sine wave to square wave at each local region

Model of parameter variations Process variations Variations on wire width and transistor length Linear variation model d = d 0 + k x x+k y y Supply voltage fluctuations Random variation (  10%) Easy to change to other more sophisticated variation models in our design framework

Multilevel Transmission Line Spiral Network

Problem Statement Formulation A: Given: model of parameter variations Input: H-tree and n -level spiral network Constraint: total routing area Object function: minimize skew Output: optimal wire width of each level spiral Formulation B: Constraint: skew tolerance Object function: minimize total routing area

Skew Reduction Effect of Transmission Line Shunts Two sources case Circuit model and skew expression Derivation of skew function Spice validation Multiple sources case Random skew model Skew expression Spice validation

Transmission line Shunt with Two Sources Transmission Line with exact multiple wave length long Large driving resistance to increase reflection

Spice Validation of Skew Equation

Multiple Sources Case Random model: Infinity long wire Input phases uniformly distribution on [0, Φ]

Configuration of Wires Coplanar copper transmission line height: 240nm, separation: 2um, distance to ground: 3.5um, width( w ): 0.5 ~ 40um Use Fasthenry to extract R,L Linear R/L~ w Relation R/L = a/w+b

Optimal Sizing of Spiral Wires Lemma: is a convex function on, where, k is a positive constant. Min: S.t.: Impose the minimal wire width constraint for each level spiral, such that the cost function is convex

Optimal Sizing of Spiral Wires Theorem: The local optimum of the previous mathematical programming is the global optimum. Many numerical methods (e.g. gradient descent) can solve the problem We use the OPT-toolkit of MATLAB to solve the problem

Experimental Results Set chip size to 2cm x 2cm Clock frequency GHz Synthesize H-tree using P-tree algorithm Set the initial skew at each level using SPICE simulation results under our variation model Use FastHenry and FastCap to extract R,L,C value Use W-elements in HSpice to simulate the transmissionlin

Optimized Wire Width Total Area W1 (um)W2 (um)W3 (um)Skew M (ps) Skew S (ps) Impr.(%) % % % % % % % % %

Simulated Output Voltages Transient response of 16 nodes on transmission line Signals synchronized in 10 clock cycles

Simulated Output voltages Steady state response: skew reduced from 8.4ps to 1.2ps

Power Consumption Area PM(mw) PS(mw) reduce(%) PM: power consumption of multilevel mesh PS: power consumption of single level mesh

AreaSkew-SSkew-M Ave.WorstAve.Worst Impr(%) % % % % % % Skew with supply fluctuation

Conclusion and Future Directions Transmission line shunts demonstrate its unique potential of achieving low skew low jitter global clock distribution under parameter variations Future Directions Exploring innovative topologies of transmission line shunts Design clock repeaters and generators Actual layout and fabrication of test chip

Derivation of Skew Function Assumptions i) G=0; ii) ; iii) Interpretation of assumptions i) ignores leakage loss ii) assumes impedance of wire is inductance dominant (true for wide wire at GHz) iii) initial skew is small

Derivation of Skew Function V i,j : Voltage of node 1 caused by source V sj independently Φ : Initial phase shift (skew) : Resulted skew Loss causes skew Lossless line: V 1,2 =V 2,2, V 2,1 =V 1,1 Zero skew

Derivation of Skew Function Summing up all the incoming and reflected waveforms to get V i,j Using first order Taylor expansion and to simplify the derivation Utilizing the geometrical relation in the previous figure, we get