1 1 Università degli Studi di Pisa, 2 INFN Pisa, 3 Scuola Normale Superiore di Pisa, 4 Università degli Studi di Pavia, 5 INFN Pavia, 6 Università degli Studi di Bergamo, 7 INFN Trieste and Università degli Studi di Trieste S. Bettarini 1,2, G. Batignani 1,2, M. Carpinelli 1,2, G. Calderini 1,2, R. Cenci 1,2, F. Forti 1,2, M. A. Giorgi 1,2, A. Lusiani 2,3, G. Marchiori 1,2, F. Morsani 2, N. Neri 2, E. Paoloni 1,2, M. Rama 1,2, G. Rizzo 1,2, G. Simi 1, J. Walsh 2, L. Ratti 4,5, V. Speziali 4,5, M. Manghisoni 5,6, V. Re 5,6, G. Traversi 5,6, L. Bosisio 7, G. Giacomini 7, L. Lanceri 7, I. Rachevskaia 7, L. Vitale 7 Vertex Chuzenji Lake, Nikko - 8 November 2005 Monolithic Active Pixel detector in 0.13 m triple well CMOS Technology (A new approach with a full analog signal processor at pixel level and an extended collecting electrode)

2 Introduction: standard CMOS MAPS for tracking in HEP The new features of our MAPS: –deep n-well collecting electrode –signal processing at pixel level Prototype characterization: –Front-End Electronics –Sensor response to: Infrared Laser soft X-ray from 55 Fe -ray from 90 Sr/ 90 Y Conclusions Outline

3 Several reasons make them very appealing as tracking devices : –detector & readout on the same substrate –wafer can be thinned down to few tens of m –radiation hardness (oxide ~nm thick) –high functional density and versatility –low power consumption and fabrication costs CMOS MAPS Principle of standard operation: The undepleted epitaxial layer acts as a potential well for electrons moving by diffusion Signal (~1000 e-) collected by the n-well/p-epi diode Charge-to-voltage conversion provided by the sensor capacitance  small collecting electrode Extremely simple in-pixel readout (3 NMOS,PMOS not allowed)  sequential readout M.I.P.:80 e-h pairs /  m

4 A new approach to MAPS The new design features of our CMOS pixels: The deep n-well can be used as the collecting electrode * A full signal processing circuit can be implemented at the pixel level overlaying the NMOS transistors on the collecting electrode In triple-well CMOS processes a deep n-well is used as a shielding frame against disturbancies from the substrate to provide N-channel MOSFETs with better insulation from digital noise * Use of the deep n-well was proposed by Turchetta et al. (2004 IEEE NSS Conference Record, N28-1) to address radiation hardness issues

5 Deep n-well sensor concept (I) Standard signal processing chain for capacitive detector implemented at pixel level: Charge-to-Voltage conversion done by the charge preamplifier The collecting electrode can be extended to obtain higher single pixel collected charge (the gain does NOT depend on the sensor capacitance) PRESHAPER DISC LATCH Elementary cell

6 Deep n-well sensor concept (II) NMOS devices of the analog section built over the deep n-well Included complementary devices needed for CMOS design Fill factor  Area(deep n-well)/Area (total n-wells) ( 0.85 in the prototype test structures) Large sensitive element crucial to maximize charge collection efficiency The readout scheme well fits into already existent architectures for data sparsification at the pixel level to improve readout speed ~43 m NMOS analog section (including input device) + collecting electrode PMOS analog section PMOS digital section NMOS digital section Shaper input MiM cap. Shaper feedback MiM cap. N-WELL DEEP N-WELL ~43 m Pixel cell layout

7 Device Simulation (ISE-TCAD) Detailed physical level simulations performed using ISE-TCAD software to: understand the charge collection mechanism and its time properties study the influence of other n-wells and the neighboring pixels optimize sensor design (3D simulation needed, in progress) Preliminary results: Single pixel collected charge ~ 1500 e- assuming p-epi  15 m thick (likely to be true) Charge collection drops rapidly out of deep n-well area ( e =10 s in the p-epi layer) Collection time: ~50 ns Uncertainties about the process: Test structure chip realized to measure some process parameters  a crucial input for simulation

8 Single devices channel 4 - pixel with large (2670 m 2 ) collecting electrode area channel 3- pixel with medium (1730 m 2 ) collecting electrode area channel 6 - pixel with small (830 m 2 ) collecting electrode area channel 5 - pixel with input pad for charge injection (830 m 2 collecting electrode area) channel 1 - pixel with input pad for charge injection channel 2 - pixel with input pad for charge injection (100 fF detector simulating capacitance) 0.13  m CMOS HCMOS9GP by STMicroelectronics: epitaxial, triple well process (available through CMP, Circuits Multi-Projets) Test Chip Layout Ch have integrated injection capacitance for readout electronics characterization

9 Pixel level charge processor High sensitivity charge preamplifier with continuous charge reset (n-well/p-epi diode leakage current) The preamplifier input provides the bias to the deep n-well (0.3 V) Input device (W/L=3/0.35) optimized for a 100 fF detector capacitance and operated at a drain current of about 1 A RC-CR shaper with programmable peaking time:0.5,1 and 2 s. Conservatively chosen to avoid ballistic deficit A threshold discriminator is used to drive a NOR latch featuring an external reset Power consumption: 10 W

10 Front-End Electronics Characterization Shaper response to a 560 e - input charge at the three different peaking times About 15% variation in peak amplitude moving from the shortest to the longest peaking time Slight overshoot probably due to residual parasitic coupling between preamplifier input and shaper output The latch preserves the signal until it has been retrieved External reset signal sent to the latch returns it to the initial condition threshold 0 1

11 Post layout simulations (PLS) within 10% of measured gain Change in the charge sensitivity probably due to loop gain degradation in the charge preamplifier (high detector capacitance, small forward gain) Charge Sensitivity (Gain) Measured in the three channels with integrated injection capacitance C D +C inj +C in C inj +C in C MIM D +C inj +C in

12 Channel 2 Channel 5 Channel 1 Equivalent Noise Charge is linear with C Tot =C D +C F +C inj +C in C D = detector capacitance(~270fF ch.5, C D MIM =100fF) C F = preamplifier feedback capacitance (8 fF) C inj = test inj. Capacitance (30 fF) C in = preamplifier input capacitance (14 fF) Equivalent Noise Charge model: S W =series white noise spectral density A f =1/f noise power coefficient A 1, A 2 =shaping coefficients dominant contribution Noise performance greatly affected by sensor capacitance actually higher than expected during the design phase. Direct measurements of p-epi/deep n-well junction capacitance on test structures confirm. Great improvement in next chip submission! Noise Measurements No significant variation as a function of t p

13 Infrared laser used to emulate charge released by a charged particle =1060 nm  abs. Coefficient~10 cm -1 in Si Total charge released equivalent to ~ 6 MIPs Charge released in a broad region under the sensor: the fraction of the charge collected by the pixel depends on the laser spot profile (not well known yet) The largest pixel collects the largest charge Charge does not scale linearly  laser spot larger than the pixel area and with non uniform profile Results roughly compatible with a gaussian laser spot profile of ~50 m Channel no.C D [fF]Charge sensitivity [mV/fC] Collected charge [e - ] Response to I.R. laser

keV line  1640 e/h pairs: charge entirely collected  clear 105 mV  gain=400 mV/fC charge only partially collected  below 100 mV excess of events w.r.t. noise only spectrum Threshold set cuts this region Peak value of the shaper output: blue - 55 Fe source (5.9 keV) green - no source (same acquisition time) Calibration with soft X-rays from 55 Fe X-ray from a 55 Fe source used to calibrate pixel noise and gain in channels with no inj. capacitance (e-)  =105 mV  =12 mV PWELLNWELL P - EPI-LAYER P ++ SUBSTRATE PWELL INCIDENT PHOTONS Charge entirely collected DEPLETION REGION Charge only partially collected by single pixel

15 Calibration results with 55 Fe Calibration with 55 Fe source in good agreement with results obtained with the inj. capacitance and within ~15% from PLS (Expected: ENC=150 e-, gain=430 mV/fC) Signal expected from M.I.P is about 1500 e- (by sensor simulation with p-epi > 15 m thick, assuming MIP most probable signal 80 e-/m) Pixel noise distribution mean=8mV Using gain measured with 55 Fe Pixel noise 8 mV ENC=125 e- S/N expected = 12

16 Response to -ray from a 90 Sr/ 90 Y source Acquisition triggered by the coincidence (scintillator AND pixel) signal above threshold, ~0.5 MIP Response to M.I.P from the beta source used to measure S/N ratio Pixel  source Scintillator Si chip 300 m e- 45% are ~ M.I.P: Landau peak 15% die in Si 40% release more than a M.I.P, they deform Landau shape or saturate the shaper Electrons from 90 Sr and 90 Y

17 Results from -ray Landau peak 80 mV (e-) saturation due to low energy particle. The spectrum clearly shows a Landau mV Using M.I.P signal and average pixel noise: S/N=10 Using gain measured with 55 Fe, M.I.P most probable energy loss corresponds to about 1250 e- Fair agreement with sensor simulation: ~1500 e- expected for p-epi layer thickness >15 m Some hint on the process secrets: p-epi layer is thick! Peak value of the shaper output: blue - with  source green - no source Threshold set cuts this region

18 First chip successfully tested! Results obtained with infrared laser and radioactive sources demonstrate the capability of the designed sensor to collect and process the charge released in the p-epi layer under the deep n-well sensitive electrode Full functionality : sensor + readout electronics Good agreement observed among various results: –Readout calibration with injection capacitance –Results from Post Layout Simulation –Response to 55 Fe and 90 Sr / 90 Y sources –Signal expected from sensor simulation The present S/N=10 is not outstanding but will be improved by about a factor 3 in the next chip (…going to arrive) –Input element of the preamplifier must be optimized for a more realistic detector capacitance (~320 fF) –Noise expected from PLS ENC ~50 e- (first chip ~150 e-)

19 A deep n-well sensor matrix is coming … (Submitted in August, expected delivery date mid-November ) 8x8 matrix (50 m pitch) + 5 single pixel channels (different collecting electrode area/smaller pixel size) ( 300  m) chips thinned down to: 150m 100m includes modified version of the charge preamplifier to address the noise issue raised by the 1st submission prototype (still) sequential readout and generation of a trigger signal as the logic sum of all of the latch outputs

20 Conclusions New CMOS MAPS detector with analog processing at pixel level fabricated in 0.13 m triple well process: –Extended size of the collecting electrode (deep n-well) with respect to the pixel area and part of the readout electronics placed over the collecting electrode to allow more complex processing at the pixel level First test chip with single pixels successfully tested with infrared laser and radioactive sources Going to arrive a pixel matrix with sequential readout and improved noise performance: S/N expected ~ 30 The final goal: to develop a matrix with sparsified readout suitable to be used in a trigger system based on associative memories This project has been funded by the Italian Ministry for Education, University and Research and will be pursued with the new SLIM (Silicon detectors with Low Interaction with Material) I.N.F.N. collaboration

21 Backup slides

22 Details on test channels

23 pepi niso Diode_niso_pepi P-well max depletion 0.4 m p-epi max depletion 3 m p+ n+ 10V ! Test structure test under way!