RS RTN CIRCUIT LEVEL ULTRA FAST CIRCUIT UPC – UAB

 CIRCUIT FOR ULTRA FAST MEASURES  CIRCUIT SETUP for RESISTIVE SWITCHING  ULTRA FAST SETUP for RESISTIVE SWITCHING  ULTRA FAST CAPTURE  PULSE SETUP  ULTRA FAST SETUP for RTN  WEIGHTED TIME LACK METHOD/PLOT (WTLM/WTLP)  TRAPPING AND DETRAPPING DETECTION  WTLM WITH ULTRA FAST SETUP  TOOLS FOR RTN CHARACTERIZATION  RTN and RS MODELING  RESISTIVE SWITCHING VARIABILITY  TOOLS for VARIABILITY and CIRCUIT PERFORMANCE  RESISTIVE SWITCHING BASED CELLS FOR CROSSPOINTS  ANNEX SUMMARY RS RTN CIRCUIT LEVEL ULTRA FAST CIRCUIT 2

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Ultra-Fast characterization circuit V DUT Device Under Test Circuit for ultra fast measures SETUP CIRCUIT Controlled by GPIB  Current limit  Ultra fast captures 4

Circuit setup for Resistive Switching 1,45 mA 215 μA 14,5 μA Control Voltage Current limit applied by hardware and controlled by voltage. 5

Typical RS characteristic Circuit setup for Resisitive Switrching V CONTROL Current limit changes between two levels controlled by the V CONTROL Current limit circuit improves the setup increasing Programming speed Current limit control Measure Resolution 6

7 RS RTN

Ultra fast setup for Resisitive Switrching Ultra fast capture Ultra fast capture Circuit allows ultra fast measures and applies the current limit during SET process. 8

Ultra fast setup with pulses SET RESET  More and faster cycles. Allows endurance sample studies.  Improves Semiconductor Analyzer setup. 9

Random Telegraph Noise RTN RTN introduces variability to the RS States, specially during HRS. RTN during HRS Top Electrode Bottom Electrode V stress “Traps” RTN is due to changes in the filament structure Device ArrayHigh Density Array Variability 10

Ultra fast setup for RTN Poor sampling resolution Ultra fast capture 11

SMU Scope Ultra fast setup for RTN Osciloscope captures by GPIB interruptions 12

(a)7.26s and 9.68s with 40µs time resolution. (b)9.68s and 12.15s with 20µs time resolution. (c)19.5s and 21.93s with 1µs time resolution. Ultra fast setup for RTN Different time window length 13

Weighted Time Lack Method/Plot More likely due to defect fluctuations in the filament, caused by stochastic atomic movements in and out of the CFs. Top Electrode Bottom Electrode V stress “Traps” Filament Conductivity Fluctuations WTLP capture 14

(Left) Typical multilevel RTN signal measured by a semiconductor parameter analyzer at Vapp=1.25V, step time ~6ms and number of measured points (Right) Trap levels obtained by using the WTLP method. Weighted Time Lack Method 15

Weighted Time Lack Plot WTLP method applied to (a) RTN measured by the SPA with 9 trap levels detected. (b) Oscilloscope capture with a time resolution of 40μs where 3 trap levels detected. (c) Oscilloscope capture with time resolution of 20μs with 3 trap levels detected. (d) Oscilloscope capture at lower time resolution of 1μs with 2 trap levels. More resolution of de Weighted Time Lack Plot with ultra fast captures 16 Fast emission and capture times not detected with SPA setup

Tools for RTN characterization Weighted Time Lag MethodUltra fast characterization Measuring capture and emission time Study variability of Resistive Switching states Extract statistics of RTN variability for modeling The combination of both tools allows: 17

18 CIRCUIT LEVEL

19  Variability sources.  Electrically minimize variability.  Variability analysis on circuit performance. Circuit Level: Objectives  Reliability issues  Architectures  Cross point structures based on RS cells.

20 RTN and RS modeling  Electrical model.  RS state represented by R value.  Bipolar RS.  Potential law for RS currents.  Easy transfer to circuit level. RS electrical model Diode – Resistance model Circuit level simulations Including variability Statistical models

Resistive Switching variability 21 RS Current Programming voltages Programming consumption VARIABILITY RTN

Resistive Switching variability 22 Programming voltage window increases as speed programming increases V SET V RESET Programming speed

Resistive Switching variability 23 Current limit Current limit favors HBD LRS more stable

Tools for variability and circuit performance analysis. RS and RTN characterization Electrical and statistical models  Pspice  Electrical models  Easy link with circuits  Simulink  Statistical parameters  Equation models (QPC)  High density circuits simulation Circuit performance analysis RRAM crossbar 24 High Density Array Device  Programming voltages  Current levels  Variability  RTN fluctuations ERROR

25 RS based cells for crosspoints Crosspoint structure MOSFET based cell Simple RS cell MOSFET based cell Any suggestions..?

Thanks!! 26

ANNEX 27

V OUT V BULK V STRESS V DUT DUT Current Limit Control Buffer I-V converter V C controls the channel current of T1, that means the current limit of the DUT Current limit applied by a transistor D2 Ultra fast setup: The circuit... 28