1 Final project Speaker: Team 5 電機三 黃柏森 趙敏安 Mentor : 陳圓覺 Adviser: Prof. An-Yeu Wu Date: 2007/1/22

2 Outline Components revising Bit numbers tuning Synthesis results  Timing & area reports Efficiency evaluation

3 64-point R2 2 SDF Counter—register, adder Shift register--register Twiddle factor --multiplier, adder, MUX BF—MUX, adder

4 Twiddle factors Goal: Reduce memories of twiddle factors  ROM table reduction by periodic and complementary sine & cosine values. Mathematical way

5 Twiddle factors (cont’d) Implementations Rules  Arrange all cases and find all sine values, write in the ROM table beforehand  Reuse  Save by absolute values, determine the sign when called out

6 Shift Registers Control Signal Instead ofUse pointer

7 Alternative Ideas Folded register (64 points) DATA

8 Alternative Ideas (cont’d) Pipeline  reduce the length of the critical path

9 Tune the Internal Bit Numbers 64-point R2 2 SDF (radix-2 2 single-path delay feedback)

10 Tune the External Bit Numbers By estimation from the architecture,  Twiddle factors have repeated and complementary values. Memories for twiddle factors can be reduced.  Shift-register is about 3 times as twiddle factors.  Output fraction part is the most critical. From the MATLAB simulation and analysis, the optimal feasible solution is (in, out, tw) = (10, 16, 10)

11 Tune the External Bit Numbers (cont’d) Input and output bits have reached the lower boundary. Twiddle factors remain 10 bits for stability.

12 Synthesis Result Timing = 15.6ns Area =

13 Conclusions Implement each component by reducing the critical paths, areas, and power consumption Score = AT 2 = 7.952*10 7 (ns 2 μm 2 )

14 [1]Weste and Harris, CMOS VLSI Design, A Circuits and Systems Perspective, 3rd Ed., Addison-Wesley, [2],Shousheng He and Torkelson, M. “A new approach to pipeline FFT processor,” Proceedings of IPPS '96, 15-19, pp766 –770. April 1996 Reference

15 Q & A Thanks for your listening!