January 11, Data Format for MICE Trackers Tracker Data Readout Basics Preliminary Tracker Data Format and Suitability for VME Data Transfers. Questions and Discussion Points Terry Hart, Illinois Institute of Technology, MICE Video Meeting

January 11, Tracker Data Readout Basics Terry Hart, Illinois Institute of Technology, MICE Video Meeting 16 Analog Front End II t (AFE-IIt) boards Inputs: Analog charge signals from 512 channels Outputs: Digital hit pattern, charge amplitudes, time amplitudes Each DFPGA connected to one of four VME LVDS Serdes Buffer (VLSB) banks. Each board contains sixteen 32-channel Trigger and Pipeline (TriP-t) chips. DFPGA AFPGA ADC TriP-t Data from VLPCs VLSB bank (4 per AFE-IIt) (4 per VLSB)

January 11, Tracker Data Readout Basics Tracker data format changed from fixed-length to variable- length to implement zero-suppression. –2 AFPGAs send data to 1 DFPGA. –Numbers of channels above threshold different for each AFPGA Filler words used in our preliminary format Each DFPGA output AFPGA data into a 21-bit words to VLSB bank. VLSB pads these to 32-bit words with status and buffer address bits. Terry Hart, Illinois Institute of Technology, MICE Video Meeting

January 11, Word Type Definitions (Preliminary) D20-18D17D D D X 110PEVENT SYNC # WORD COUNT X 101PDATA X 100PDATA X 011P DATAX 010P X X VLSB Trigger Word Header Word Data Word Data w/t filler LO Data w/t filler HI Fill Word VLSB Null Word P = parity bitX = Serdes sync bit These 21-bit words form events which encode the tracker data. Terry Hart, Illinois Institute of Technology, MICE Video Meeting AFPGA0 Data AFPGA1 Data

January 11, P = parity bitX = Serdes sync bit Sample Event X 110PEvent Sync #Word CountX 101 PAFPGA0 Bitmap DATA AFPGA0 Bitmap DATA AFPGA1 Bitmap DATA AFPGA1 Bitmap DATA X 101 PChannel DATA TriP0 time DATA TriP1 time DATA TriP0 charge DATA Trip1 charge DATA FILLER (no hits for AFPGA1) X VLSB trigger word Header word Bitmap words Channel readout Terry Hart, Illinois Institute of Technology, MICE Video Meeting AFPGA0 Data AFPGA1 Data

January 11, Can VME Handle Data Rate With Single Word Transfers? For 0.5% channel occupancy for 128 channels in a DFPGA, –53% of 64 DFPGAs have zero hits (10 words) –34% of 64 DFPGAs have one hit (15 words). –11% of 64 DFPGAs have two hits (15 or 20 words). – 2% of 64 DFPGAs have three hits (20 or 25 words). This yields average event size of ~1000 words for 64 DFPGAs. At 600 events/ms, 600,000 words need to be read out each 1 second between spills. Terry Hart, Illinois Institute of Technology, MICE Video Meeting

January 11, Can VME Handle Data Rate With Single Word Transfers? At 600 events/ms, 600,000 words need to be read out each 1 second between spills. Assume 4 VME crates for 125,000 words/crate/sec. –Each VME word transfer takes ~ 1 µs –Total time ~ sec << 1 sec between spills. (32-bit DMA transfers can roughly double this rate.) Single word transfers seem to be sufficient to empty VLSB memory. Terry Hart, Illinois Institute of Technology, MICE Video Meeting

January 11, Discussion Points Are VME single word transfers suitable for MICE VLSB readout? –Or 32-bit block transfer? –Need support for 64-bit block transfers? Event aggregation needed? Does MICE need uniform header word and word count conventions? Trigger word for every event or only for start of 1-ms wide spill? Do we need to squeeze out filler words? Terry Hart, Illinois Institute of Technology, MICE Video Meeting