October 10, 20001

2 USB 2.0 Host Controllers (EHCI Specification) John S. Howard Intel Corporation

October 10, Agenda w Project Overview w Key Features Overview – USB 2.0 Host Controller Architecture – EHCI HC Interface Architecture – EHCI HC Data Structures – Operational Models (Overview/Examples) w Host Controller Compliance Program w Summary

October 10, Project Overview w Intel developed specification with contributions from – NEC, Lucent, Philips, Compaq and Microsoft – Licensees ** can also contribute to specification w Enhanced Host Controller Specification for USB – Defines the architecture for a USB 2.0 capable host controller, and – Defines register (hardware/software) interface for a high-speed capable host controller

October 10, Project Overview w Public revisions will be available soon – Each revision comes with a license agreement – Revision 0.95 will be the first public release u License agreement provides reciprocal royalty free license to manufacture compliant discrete USB 2.0 host controllers based on this specification – Revision 1.0 is the final specification u License agreement provides reciprocal royalty free license to manufacture compliant USB 2.0 host controllers based on this specification Continued

October 10, USB 2.0 Host Controller Architecture w Multi-function Controller delivers 3 port speeds – Simplifies High-speed Host Controller u Optimize for high-speed functionality – Reuses USB 1.1 Host Controller Designs (drop-in) – USB ports work independent of high-speed capable software USB 2.0 Host Controller (HC) Port 1 Companion USB HCs for FS/LS Port 1 Port 2 Port Owner Control(s) Port 1 Port 2 Port Routing Logic Port N HC Control Logic/Data Buffering Enhanced HC Control Logic Enhanced Data Buffering Port 2 Port N High-Speed (Enhanced Interface) USB HC

October 10, USB 2.0 Host Controller Architecture: Port Routing Rules w Ports owned by Companion controllers when HS HC software is absent w When HS HC Software is present, it “configures” High-Speed HC then: – Retains ownership for high-speed devices – Releases individual port ownership if attached device is not high speed u Routing Logic signals a disconnect on HS HC and a connect on Companion HC – Ownership returns to HS HC on a disconnect event Companion USB 1.1 HC X Port Register High Speed HC (EHCI) (EHCI) TransceiverTransceiver Port Routing Logic Port Owner Control HC Configured Port Register

October 10, EHCI Interface Architecture (Overview) Capability Registers Operational Registers Memory-Based I/O Registers PCI Class Code, etc. USB Base Address PCI Power Management Interface PCI Configuration Register Shared Memory Work Lists Periodic List Asynchronous List

October 10, Operational I/O Registers w Command/Configuration – Management of HC, schedules on/off, etc. w Status w Interrupt Management w Schedule Management – Periodic Base Pointer – Frame Index – Asynchronous List Pointer w Port Status and Control

October 10, Agenda w Project Overview w Key Features Overview – USB 2.0 Host Controller Architecture – EHCI HC Interface Architecture – EHCI HC Data Structures – Operational Models (Overview/Examples) w Host Controller Compliance Program w Summary

October 10, EHCI Data Structures w Five (5) basic data structures (schedule objects) – Queuing Data Structure (2) – High-speed isochronous (1) – Full-speed isochronous (1) – Frame List (1) w Used to build construct Periodic and Asynchronous Schedules w All data structures support simple data buffer scatter/gather

October 10, Queuing Data Structures Overview w Queues are used for ALL Non-Isochronous transfers w Uses 2 data structures: – qHead and a qElement w 1 queue per endpoint w Each queue element (transaction descriptor) describes a buffer (1 to many transactions) – Up to 20 Kbytes per transaction descriptor u 16Kbytes with worst-case buffer alignment w No Hardware/software sync required to add work to a queue w Architecture optimized to provide efficient memory accesses – Block, burst accesses – Efficient, cache execution model

October 10, HS Isochronous Data Structure Overview w HS Isochronous use isochronous Transfer Descriptors (iTDs) w Linked into periodic schedule (made ‘reachable’ in the appropriate frames) w Time-oriented data structure – “Frame number” encoded in topology of list – No hardware (micro)-frame arithmetic required – Position of work item in periodic list determines when it will be “seen” and executed by the host controller w 8 transaction descriptions per iTD w Supports High-bandwidth w Supports up to 28K bytes per iTD w Requires multiple iTDs to maintain HS isochronous data stream Buffer pointer Array Next Transaction Record Description Array (8) Endpoint Information Isochronous Transfer Descriptor (iTD)

October 10, FS Isochronous Data Structure Overview w FS Isochronous uses split isochronous Transfer Descriptors (siTDs) w Similar usage and behavioral model as iTDs, except: w Will only use split transactions w 1 FS transaction per siTD – Linked in one siTD per Frame w Supports one page boundary w Appropriate mechanisms to care and feed isoch split transaction Next Endpoint Info. Transfer State Buffer pointer(s)

October 10, Periodic Frame List w Array of schedule object pointers w Represents a rolling window of time – Each location is base pointer for one frame’s worth of work (8 micro- frames) – Frame work for establishing time oriented reachability w HC builds a Periodic Frame list address from: – Periodic frame list base address – Frame Index Register [12:3] u increments once each frame (1ms) Frame List Base Frame Index Periodic Frame List … To schedule graph Accesses same offset 8 micro- frames before preceding to next location

October 10, Agenda w Project Overview w Key Features Overview – USB 2.0 Host Controller Architecture – EHCI HC Interface Architecture – EHCI HC Data Structures – Operational Models (Overview/Examples) w Host Controller Compliance Program w Summary

October 10, EHCI Operational Models w Asynchronous Schedule Overview w Queuing example operation w Periodic Schedule Overview w HS Isochronous w HS Interrupt w Asynchronous split transactions w Periodic split transactions

October 10, Current qHead Pointer Asynchronous Schedule Overview w Schedule includes only Queue Heads w Organized in simple, circular list w Manages HS/FS/LS asynchronous endpoints w Yields Round-Robin Service Order w Supports FS/LS asynchronous I/O Register: Asynchronous List Pointer

October 10, Queuing Example Operation Transfer Descriptors Linked to queue head by software driver Transfer Descriptors Linked to queue head by software driver qTD 0 qTD 2 Data Buffer 0 Data Buffer 1 qTD 1 Data Buffer 2 Queue Head: Static queue head information Dynamic transfer execution area Queue Head: Static queue head information Dynamic transfer execution area SetupSetup StatusStatus Setup Data Receive Data Buffer DataData Example: Control Transfer Initial Condition: QHD empty Example: Control Transfer Initial Condition: QHD empty Example: Control Transfer Software attaches list to QHD Example: Control Transfer Software attaches list to QHD Current (A) (A) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Setup Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD for 1 transaction Next (B)(B) (B) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Data Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD until done (B) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Data Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD until done CurrentCurrent CurrentCurrent NextNext (C) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Status Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD for 1 transaction (C) HC Finds an active qTD via a QHD Next pointer and copies to overlay area (Status Stage) Copy results in QHD Next pointer inheriting from overlay’d qTD HC executes from QHD for 1 transaction (C)(C)

October 10, Periodic Schedule Overview w Periodic Frame List is the base – Size is optionally programmable w Objects linked so are ‘reachable’ at the correct time w Schedule graph includes: – Queue Heads for Interrupt – HS Isochronous, – FS Isochronous Poll Rate: N  1 Periodic Frame List End of List Mark 4 2 Periodic List Base + Frame Index[12:3] = current Frame offset

October 10, Frame Index [2:0] bits serve as index to select a transaction record; e.g. a value of 010b will select transaction record #2. If the Status.Active field of selected transaction record is a one, then a transaction will be executed Frame Index HS Isochronous Example Operation Starting data buffer is derived from: x = FRAME INDEX[2:0] BufferPageA[tRec[x].PG] concatenated with tRec[x].TransactionOffset Token is derived from EndPt and Device Address fields. Length of the transaction is: tRec[x].TransactionLength or Max Packet Size field, whichever is less. Direction of transfer is determined by the I/O field. Host controller decrements Transaction Length by the number of bytes moved, and updates the Status field appropriately.Concat. Buffer pointer Array Next Transaction Record Description Array (8) Endpoint Information Isochronous Transfer Descriptor (iTD)

October 10, HS Interrupt w Uses queuing data structures – No change to behavioral model w Linked into periodic schedule (made ‘reachable’ in the appropriate frames) – HS poll rates are micro-frames – Embedded bit-mask in qHead describes micro-frame pattern w Simple mechanism to support high-bandwidth

October 10, Asynchronous Split Transactions w Micro-machine extension to the HS queue execution model – HS transfer advancement occurs when HS transaction is complete – FS/LS transfer advancement occurs when start-split and complete splits are complete w Endpoint speed encoding directs HC to use split protocol w All other behavior same as HS asynchronous

October 10, Periodic Split Transactions w Used to service data streams through TT periodic pipelines w Requirement on HC is to: – Execute starts and completes when they need to occur w Each endpoint data structure contains: – Masks for Starts/Completes – Micro-state to track progress (to detect lost data, etc.) w Projection of core-spec bus frame boundaries into the host schedule created many scheduling boundary conditions, so…

October 10, Mapping Bus Frames to Host Frames w In order to simplify host for TT pipeline support: – Host view of frame boundaries is shifted one micro-frame

October 10, FS/LS Interrupt IN Example Operation Start-Mask40h Complete-Mask03h H-Frame B-Frame7 Queue Head SS CS 0 CS 1 Reachable from Frame list locations: 0,1, 8,9, 16,17 … (poll period of 8)

October 10, FS Isochronous IN Example Operation Start-Mask08h Complete-MaskC3h H-Frame X B-Frame 7 siTD X SS CS 0 CS 1 CS 2 CS 3 H-Frame X+1 siTD X+1

October 10, Agenda w Project Overview w Key Features Overview – USB 2.0 Host Controller Architecture – EHCI HC Interface Architecture – EHCI HC Data Structures – Operational Models (Overview/Examples) w Host Controller Compliance Program w Summary

October 10, EHCI Compliance Program EHCI Compliance Standard USB 2.0 Compliance Tests EHCI-specific Functional Testing Data Integrity Basic Feature Function Singleton Streaming Streaming Interoperability Stress USB 2.0 Electricals (HS/FS/LS) Hub Tests

October 10, EHCI Compliance Program w EHCI-specific compliance software under development at Intel w Special compliance devices (high-speed and full/low speed) w Special-purpose application and driver for controlled testing and analysis w Interface Functional Testing – Device Interoperability – USB 2.0 protocol and transfer extensions – System Interaction – Etcetera, … EHCI Compliance Application EHCI Compliance Test Driver EHCI Unit Under Test USB 2.0 Hub (s) HS Compliance Device(s) FS/LS Compliance Device (s)

October 10, EHCI Compliance Program w Test Availability w HC compliance test will be available from Intel – Method of distribution (to be defined) w Alpha-level tools available in Q w Beta-level tools available in Q w Production release available with release of 1.0 EHCI host controller specification in Q3 Note: all dates provided are for planning purposes only and are subject to change

October 10, Summary w Low-risk Introduction – All ports are HS/FS/LS Capable – Legacy (non-high-speed aware) software just works – Re-use of 1.1 controllers simplifies high-speed controller w Interface optimized for good memory access efficiency w Reasonable tradeoff of hardware/software complexity

October 10, Summary w Host controller compliance program – Alpha release Q1, 2001 – Beta release Q2, 2001 – Final with 1.0 EHCI Specification w Specification Revisions available: – Revision 0.95 for discrete HC Q – Revision 1.0 in 2001 u Gating item is validation of integrated host controller Continued Note: all dates provided are for planning purposes only and are subject to change