Hybrid Approach to Model-Checking of Timed Automata DAT4 Project Proposal Supervisor: Alexandre David.

Slides:



Advertisements
Similar presentations
Auto-Generation of Test Cases for Infinite States Reactive Systems Based on Symbolic Execution and Formula Rewriting Donghuo Chen School of Computer Science.
Advertisements

1 Title Page Implicit and Explicit Reachable State Space Exploration Of Esterel Logical Circuits Advisor :
Real-Time Systems, DTU, Feb 15, 2000 Paul Pettersson, BRICS, Aalborg, Denmark. Timed Automata and Timed Computation Tree Logic Paul Pettersson
UCb Symbolic Reachability and Beyound or how UPPAAL really works Kim Guldstrand Larsen
A Survey of Runtime Verification Jonathan Amir 2004.
1 Fault Diagnosis for Timed Automata Stavros Tripakis VERIMAG.
Automatic Verification Book: Chapter 6. What is verification? Traditionally, verification means proof of correctness automatic: model checking deductive:
Verification of Graph Transformation Systems Arman Sheikholeslami
Game-theoretic approach to the simulation checking problem Peter Bulychev Vladimir Zakharov Lomonosov Moscow State University.
ECE 720T5 Fall 2011 Cyber-Physical Systems Rodolfo Pellizzoni.
UPPAAL Introduction Chien-Liang Chen.
Hybrid Systems Presented by: Arnab De Anand S. An Intuitive Introduction to Hybrid Systems Discrete program with an analog environment. What does it mean?
Timed Automata.
Introduction to Uppaal ITV Multiprogramming & Real-Time Systems Anders P. Ravn Aalborg University May 2009.
UPPAAL Andreas Hadiyono Arrummaisha Adrifina Harya Iswara Aditya Wibowo Juwita Utami Putri.
CSE 522 UPPAAL – A Model Checking Tool Computer Science & Engineering Department Arizona State University Tempe, AZ Dr. Yann-Hang Lee
ESE601: Hybrid Systems Some tools for verification Spring 2006.
Efficient Reachability Analysis for Verification of Asynchronous Systems Nishant Sinha.
Verification of Hybrid Systems An Assessment of Current Techniques Holly Bowen.
Compatibility between shared variable valuations in timed automaton network model- checking Zhao Jianhua, Zhou Xiuyi, Li Xuandong, Zheng Guoliang Presented.
Digitaalsüsteemide verifitseerimise kursus1 Formal verification: Property checking Property checking.
Vending Machine Specifications State Machine GUI Comments.
Reachability Analysis for Some Models of Infinite-State Transition Systems Oscar H. Ibarra, Tevfik Bultan, and Jianwen Su Department of Computer Science.
Bounded Model Checking EECS 290A Sequential Logic Synthesis and Verification.
Verification and Controller Synthesis for Timed Automata : the tool KRONOS Stavros Trypakis.
CaV 2003 CbCb 1 Concurrency and Verification What? Why? How?
Starting Introduction Project description Project demonstration Conclusion Question.
Embedded Systems Laboratory Department of Computer and Information Science Linköping University Sweden Formal Verification and Model Checking Traian Pop.
1 Completeness and Complexity of Bounded Model Checking.
1 Verification Options & Beyond Reachability or how to make UPPAAL perform better and more Kim Guldstrand Larsen
Timing analysis of an SDL subset in UPPAAL Anders Hessel Institution of Information Technology Department of Computer Systems Uppsala University M.Sc.
1 Efficient Verification of Timed Automata Kim Guldstrand Larsen Paul PetterssonMogens Nielsen
02/06/05 “Investigating a Finite–State Machine Notation for Discrete–Event Systems” Nikolay Stoimenov.
UPPAAL Ghaith Haddad. Introduction UPPAAL is a tool for modeling, validation and verification of real-time systems. Appropriate for systems that can be.
ECE 720T5 Winter 2014 Cyber-Physical Systems Rodolfo Pellizzoni.
Data Representation A series of eight bits is called a byte. A byte can be used to represent a number or a character. As you’ll see in the following table,
Transformation of Timed Automata into Mixed Integer Linear Programs Sebastian Panek.
Software Engineering Research paper presentation Ali Ahmad Formal Approaches to Software Testing Hierarchal GUI Test Case Generation Using Automated Planning.
Dina Workshop Analysing Properties of Hybrid Systems Rafael Wisniewski Aalborg University.
Selected Topics in Software Engineering - Distributed Software Development.
Generic API Test tool By Moshe Sapir Almog Masika.
1 Hybrid-Formal Coverage Convergence Dan Benua Synopsys Verification Group January 18, 2010.
Lecture51 Timed Automata II CS 5270 Lecture 5.
Lecture 81 Regional Automaton CS 5270 Lecture 8. Lecture 82 What We Need to Do Problem: –We need to analyze the timed behavior of a TTS. –The timed behavior.
Timed I/O Automata: A Mathematical Framework for Modeling and Analyzing Real-Time Systems Frits Vaandrager, University of Nijmegen joint work with Dilsun.
1 Outline:  Optimization of Timed Systems  TA-Modeling of Scheduling Tasks  Transformation of TA into Mixed-Integer Programs  Tree Search for TA using.
1 CSEP590 – Model Checking and Automated Verification Lecture outline for August 6, 2003.
Scheduling Lacquer Productions with Uppaal AXXOM case study of the Ametist project Angelika Mader Distributed and Embedded Systems Group, University of.
1 Model Checking of of Timed Systems Rajeev Alur University of Pennsylvania.
Verification & Validation By: Amir Masoud Gharehbaghi
Abstract Priority-based FRP (P-FRP) is a functional programming formalism for reactive systems that guarantees real-time response. Preempted tasks in P-FRP.
Symbolic Algorithms for Infinite-state Systems Rupak Majumdar (UC Berkeley) Joint work with Luca de Alfaro (UC Santa Cruz) Thomas A. Henzinger (UC Berkeley)
ECE/CS 584: Verification of Embedded Computing Systems Model Checking Timed Automata Sayan Mitra Lecture 09.
TESTCOM/FATES Test Plan Generation for Concurrent Real-Time Systems based on Zone Coverage Analysis Farn Wang Dept. of Electrical Eng. National Taiwan.
1 Budapest University of Technology and Economics Department of Measurement and Information Systems Budapest University of Technology and Economics Fault.
CS5270 Lecture 41 Timed Automata I CS 5270 Lecture 4.
UPPAAL Real-Time Systems Lab. Seolyoung, Jeong.
The Time-abstracting Bisimulation Equivalence  on TA states: Preserve discrete state changes. Abstract exact time delays. s1s2 s3  a s4  a 11 s1s2.
Dept. of Nuclear and Quantum Engineering
Introduction to Formal Verification
SS 2017 Software Verification Timed Automata
Timed Automata II CS 5270 Lecture Lecture5.
Instructor: Rajeev Alur
On Using Linearly Priced Timed Automata for Flow Analysis
Timed Automata Formal Systems Pallab Dasgupta Professor,
Introduction to Formal Verification
Discrete Controller Synthesis
Alan Mishchenko UC Berkeley
Alan Mishchenko UC Berkeley
State Abstraction Techniques for the Verification of Reactive Circuits
Presentation transcript:

Hybrid Approach to Model-Checking of Timed Automata DAT4 Project Proposal Supervisor: Alexandre David

What is Model-Checking? Idea: You define a model in a given formalism/language (TA). You give specifications in the form of formulas in a given logic (TCTL). … in a tool (UPPAAL). You press a button and: Yes, properties are satisfied (and why). No, properties are not satisfied (and why).

What is UPPAAL? Tool developed between Uppsala University and Aalborg University. Model-checker for Timed Automata. It has a graphical interface to draw the TA = state machines with clock constraints.

UPPAAL The GUI (java): Editor. Simulator. Verifier. The server (C++): Verification engine (model-checker).

Timed Automata in a Nutshell! Lamp User Off LowHigh push! push? Closed system controller environment x>5 x<=5 x=0

TA in UPPAAL Templates to define processes. Parameters. States have invariants (progress). Access to integer variables and C-like functions and syntax.

So What’s The Problem? Model-checking here: Enumerate all the possible states = State-space exploration (enumerative!). But… size of the state-space = # of locations in every process * # of possible values for every variable * # of different (not included) zones. And that’s not good! Known as state-space explosion.

Zones Symbolic representation of clock constraints = difference bound matrices (DBMs). Size = (clocks+1) 2, # of zones?

Example Size of the state-space is approximately 4*4*4*4*4 (=2 10 ) * 2 (1 binary variable) * # of zones for 5 clocks (DBM 6x6) in this model ~ 4 possible values/clock to simplify = 2 10 = 2 21 states! Memory: integers per state = 168 bytes -> 336MB. Add 1 process: *4*4…

Don’t Panic! All the states are not reachable! Synchronizations and conditions between processes. The system implements some logic, it does not generate everything… but we still have the explosion.

What’s The Project? Big fat state-space Initial state Goal state Find a path But how? Breadth first search.

Project Idea Help the search by pruning the state- space! Cheap backward reachability with an over-approximation. Use the result to prune the search forward!

The Idea! Big fat state-space Initial state Goal state Pruned!

Hybrid Approach Use a backward search with an approximation technique (BDD or whatever). Use the forward exact search and pruning.