Design center Vienna Donau-City-Str. 1 A-1220 Vienna Vers SVEN Scalable Video Engine Gerald Krottendorfer

SVEN – Decoder/Encoder SVEN – Scalable Video Engine Video Decoder/Encoder Fully programmable: multistandard / multiformat: MPEG-2 MPEG-4 H.264 WMV9/VC-1

Architecture

SVEN Architecture

SVEN

Video Processor SVEN

Stream Processor SVEN

Memory Controller SVEN

Requirements  Programmable  Processing Power  Bandwidth  Scalability Video Decoder/Encoder: Programmable Processing power Bandwidth Scalability

Programmable Processing power Bandwidth Scalability Multi standard compliancy: H.264 VC-1 MPEG-2 MPEG4 DIVx etc. … High complexity of application Standard compliancy tests after TO Minimize design risks & time to market Increased flexibility

Processing Power Enhanced compression standards: H.264, VC-1: higher compression rates at substantially higher processing power requirements High processing power requirements In combination with High Definition Digital TV Standards: VERY high processing power needs Programmable Processing power Bandwidth Scalability

Scalable Processor application Processing Power Decoder + Encoder Decoder + Image processing Decoder Programmable Processing power Bandwidth Scalability H.264 MPEG-4 MPEG-2 decoding standard

Power & Core Size PowerArea Power and Area Scales with Processing power requirements Programmable Processing power Bandwidth Scalability

Bandwidth Requirements H.264 H VERY High Databandwidth Needs Bitstream Decoder IQ + IITrans Inter/intra prediction 94MB/s Memory Controller 94MB/s 490MB/s DRAM 20 Mbit/s Parameter Deblocking 94MB/s 250MB/s220MB/s Programmable Processing power Bandwidth Scalability

Solution  Programmable  Processing Power  Bandwidth  Scalability Video Decoder/Encoder: Programmable Processing power Bandwidth Scalability

Control ProcessorController Dual Core Solution Dual Core Architecture: Control Processor:   stream parsing   data flow control   HW accelerator   Datapath: ALU (RISC) VIDEO Processor:   Transform operation   inter / intra prediction   filtering   Datapath: MAC (DSP) Video Processor Number Cruncher Programmable Bandwidth Scalability Processing power

Programmable Processing power Bandwidth Scalability SVEN SVEN Processing Power H.264 Decoder / picture format enhanced DTV HDTV Film 1080i/720p Main Profile Standard DSP Performance Limit ADI Blackfin TI C64 D1 720x486 Baseline profile dual Blackfin Embedded DSP Performance Limit CIF 352x288 Baseline Equator SVEN SVEN SVEN Performance

--- Scalable Architecture --- DSP Programmable Processing power Bandwidth Scalability Linear Scalability effective processing power scalable Architecture R * N DSP/RISC Architecture R / [ (1-k) + k/N ] Legend: N = Number of parallel computing entities R = processing power of a single computing entity k = factor from 0 to 1, determining the percentage of commands which can be parallelized Scalability SVEN versus DSP: Scalability

Bandwidth   Flexible data exchange in between Slices due to cross matrix REG SLICE 0 SLICE 1 REG SLICE N Streamline Bus Broadcast Bus Cross Matrix   Data Transport in between Slices/Slots does not steal processing performance Processing Power Programmable Processing power Scalability Bandwidth

I/O Capabilities Programmable Processing power Scalability Bandwidth   Stream Processor: Each Slot has its own Data memory SLOT 0 DATA_MEM SLOT 1 SLOT N DATA_MEM

I/O Capabilities Programmable Processing power Scalability Bandwidth   Video Processor: Each Slice has its own Data memories   Stream Processor: Each Slot has its own Data memory SLICE 0 DATA_MEM A SLICE 1 SLICE N DATA_MEM B DATA_MEM A DATA_MEM B DATA_MEM ADATA_MEM B

Programmable Processing power Scalability Bandwidth DMA Access SLICE 0 DATA_MEM A SLICE 1 SLICE N DATA_MEM B DATA_MEM A DATA_MEM B DATA_MEM A DATA_MEM B DMA ENGINE DMA IF   Direct Access to Video Buffer from all Slices via DMA port at each Slice Data Memory   Video Processor: Each Slice has its own 2 Data memories   Stream Processor: Each Slot has its own Data memory

Programmable Processing power Scalability Bandwidth Scalable Bandwidth   Direct Access to Video Buffer from all Slices via DMA port at each Slice Data Memory   Video Processor: Each Slice has its one 2 Data memories   Stream Processor: Each Slot has its one Data memory Scalable Data Bandwidth

Roadmap VSP IP available H.264 VC-1 MPEG4 DivX MJPEG JPEG2000 etc... MPEG SVEN IP available SVEN IP Proof of concept: Manufactured IC VSP S8-32 Proof of concept: Manufactured IC Library / Applications IP-Core IP core shipping

Programming Toolchain Controller-Debugger SVEN-Debugger Eclipse based IDE Simulator / Debugger Assembler / C-Style Code Compiler Allows integration of external Processor cores (Host, Audio DSP)

Case Study

Multistandard HDTV Decoder   HDTV compliant 1080i60 … 30 fps 720p60 … 60fps   Multistandard Decoder MPEG2 H.264 VC-1 Requirements:

Core Size & Power Core Area [mm 2 ] Code Memory Data Memory Video Processor7.764k128k Stream ProcessorCore: 1.564k8k Extension: 1.4 (CABAC, VLC) Memory Controller0.6-- Power750 mW Technology: 130nm TSMC Clockspeed: 200MHz

Summary Fully Programmable All video formats: H.264, VC-1, MPEG-2,... Scalable Architecture Enables software programmable HDTV video codec Small Core Size / Low Power For high volume markets

ON DEMAND Microelectronics Design Center Vienna Techgate, Donau-City-Str.1 A-1220 Vienna / Austria