DEPFET detectors for future colliders. Activities at IFIC, Valencia Terceras Jornadas sobre la Participación Española en los Futuros Aceleradores Lineales de Partículas Universitat de Barcelona C. Mariñas, IFIC, CSIC-UVEG Carlos Mariñas, IFIC, CSIC-UVEG

Outlook General requirements for future colliders DEPFET: Fundamentals DEPFET: Basics Characterization: Matrices: PXD4/PXD5/PXD6 production Single Pixel Test Beam Data analysis ILC simulation (see M. Vos talk) Thermal studies ILC/SuperBelle DEPFET thermal mock-up Simulation DEPFET activities at IFIC Pixel detectors for future colliders IFIC in the DEPFET Collaboration Conclusions C. Mariñas, IFIC, CSIC-UVEG

Vertexing in future colliders C. Mariñas, IFIC, CSIC-UVEG  This requirements impose unprecedented constraints on the detector: High granularity Fast read-out Low material budget Low power consumption  This requirements impose unprecedented constraints on the detector: High granularity Fast read-out Low material budget Low power consumption  Vertexing in future colliders requires excellent vertex reconstruction and efficient heavy quark flavour tagging using low momentum tracks DEPFET  Measurements made on realistic DEPFET prototypes have demonstrated that the concept is one of the principal candidates to meet these challenging requirements DEPFET  Measurements made on realistic DEPFET prototypes have demonstrated that the concept is one of the principal candidates to meet these challenging requirements

DEPFET principle C. Mariñas, IFIC, CSIC-UVEG  Each pixel is a p-channel FET on a completely depleted bulk  A deep n-implant creates a potential minimum for electrons under the gate (internal gate)  Signal electrons accumulate in the internal gate and modulate the transistor current (400pA/e - )  Accumulated charge can be removed by a clear contact  Each pixel is a p-channel FET on a completely depleted bulk  A deep n-implant creates a potential minimum for electrons under the gate (internal gate)  Signal electrons accumulate in the internal gate and modulate the transistor current (400pA/e - )  Accumulated charge can be removed by a clear contact Fully depleted Large signal Fast signal collection Low capacitance, internal amplification Low noise Transistor ON only during readout Low power Complete clear No reset noise Fully depleted Large signal Fast signal collection Low capacitance, internal amplification Low noise Transistor ON only during readout Low power Complete clear No reset noise

Introducing the Valencia’s set up Faraday cage PC for data acquisition Stack of power supplies Laser Motorstages XYZ Complete system for air and liquid cooling ◦Cooling blocks ◦Aluminium coils Pulse generator C. Mariñas, IFIC, CSIC-UVEG

Matrix characterization C. Mariñas, IFIC, CSIC-UVEG  Full electrical optimization of matrices: This implies scans over a wide range of the operating voltages to achieve the best signal-to-noise ratio. Clear High/Low Gate ON/OFF Back Bulk Cleargate Source  Full electrical optimization of matrices: This implies scans over a wide range of the operating voltages to achieve the best signal-to-noise ratio. Clear High/Low Gate ON/OFF Back Bulk Cleargate Source  Calibration of the system using radioactive sources Gain of the system ENC  Calibration of the system using radioactive sources Gain of the system ENC  Laser scans: Charge collection uniformity

Already tested at IFIC PXD4 CLGClocked Cleargate NHE 38x30μm 2 PXD5 CCGCommon Cleargate LE 32x24μm 2 Future PXD6? C3GCapacitive Coupled Cleargate 24x24μm 2 ILC design C. Mariñas, IFIC, CSIC-UVEG

DEPFET Single-pixel (under construction) D1 D2 S G1 G2Cl Clg Blk Clg C. Mariñas, IFIC, CSIC-UVEG Inner structureSet-up Better understanding of new structures Different geometries (L- gate) Implants Better understanding of new structures Different geometries (L- gate) Implants Direct access to the system’s parameters Complete clear Charge collection Noise Direct access to the system’s parameters Complete clear Charge collection Noise

Test Beam C. Mariñas, IFIC, CSIC-UVEG

Test Beam: Our role C. Mariñas, IFIC, CSIC-UVEG Full electrical characterization of one DUT Participate in the assembly and allignment of the telescope Parallel set-up in control room Analysis of data Test Beam Coordinators 2008 and 2009 (M.Vos) BEAM 120 GeV ∏ x y z

Test Beam: Measurements Voltage scans: Cross-check optimal settings ◦V Bias to the wafer V ◦V Edge ◦V ClearHigh Angular scan: Resolution vs. Cluster size ◦-5, -4, -3, -2, -1.5, -1, -0.5, 0, 0.5, 1, 1.5, 2, 3, 4, 5, 6, 9, 12, 18, 36 Beam energy scan: Separation “multi-scattering- intrinsic resolution” ◦20, 40, 60, 80, 120 GeV Large statistics ◦Charge collection uniformity ◦3 Mevents in nominal conditions C. Mariñas, IFIC, CSIC-UVEG

T.B. Data analysis C. Mariñas, IFIC, CSIC-UVEG d0 (32x24) d1 (32x24) d2 (24x24) d3* (32x24) d4 (32x24) d5 (32x24) Sig3x3(ADU) Noise (ADU)12,713,412,713,412,813,2 SNR SeedSignal(A DU) 69%56%59%61%63%64% ENC (e - ) g q (pA/e - ) Preliminary Seed signal Preliminary Residual  MS  Tel  Int, m) Beam Energy (GeV) Distance (m) Entries  total =2,5m

Thermal studies: Simulation and measurements C. Mariñas, IFIC, CSIC-UVEG First DEPFET thermal mock-up Thermal simulation

C. Mariñas, IFIC, CSIC-UVEG  Thermal measurements  Influence of conduction  T of cooling blocks  Bump bonding  Influence of convection  Air speed  Air temperature  Study of new materials  Thermal measurements  Influence of conduction  T of cooling blocks  Bump bonding  Influence of convection  Air speed  Air temperature  Study of new materials Power (W) Temperature (ºC) Air speed (m/s) Temperature (ºC) T normalized (K/mm 2 ) Power (W) New materials

C. Mariñas, IFIC, CSIC-UVEG  Thermal simulation  Model implemented in SolidWorks for future mechanical studies  ANSYS studies calibrated with real data  Thermal simulation  Model implemented in SolidWorks for future mechanical studies  ANSYS studies calibrated with real data

A couple of movies… C. Mariñas, IFIC, CSIC-UVEG Switching mechanism is introduced Influence of air and liquid cooling studies

Conclusions Vertexing in Future Colliders ◦Very hard conditions  Radiation (10MRad for SuperBelle)  Background  Reduced material budget  Unprecedented granularity  Power consumption and heat dissipation ◦Improvement of the detector’s performance is needed New generation of pixel detectors try to cope with this requirements DEPFET: One of the most promising technologies for vertexing and tracking C. Mariñas, IFIC, CSIC-UVEG

Conclusions: DEPFET in Valencia C. Mariñas, IFIC, CSIC-UVEG Matrix characterization ◦2 different generations characterized ◦Full electrical optimization ◦Calibration ◦Charge collection uniformity ◦Working on Single Pixel set-up Test Beam ◦Optimization of DUT ◦Instalation and alignment of the telescope ◦Data analysis Thermal studies ◦DEPFET thermal mock-up ◦Study of new materials for better cooling ◦Influence of air/liquid cooling ◦Simulation

Backup slides C. Mariñas, IFIC, CSIC-UVEG

Mechanics 1. Support structures: ◦FEA models of mechanical properties  Natural frequencies  Rigidity  Stability  Deformations ◦Validation with mock-up 2. Module: ◦Simulations using FEA: ( Finite Element Analysis )  Mechanical effects: Strenght of module  Thermal effects: Cooling ◦Validation with prototypes C. Mariñas, IFIC, CSIC-UVEG

Competitors for SuperBelle Strip detectors (DSSD) Shorter strips Fast readout (higher noise) Cannot be thinned Hybrid pixel detectors (ATLAS type) Good readout speed and granularity Too much material Pixel detectors with frame readout High granularity Low mass (50 microns) Slow frame readout (rolling shutter) C. Mariñas, IFIC, CSIC-UVEG DEPFET

Competitors for ILC CCD Small signal Cryogenic operation Radiation damage (trapping) CMOS sensors: MAPS/CAPS Only small chips possible Dead material in periphery Silicon On Insulator (3D integration) Thick depleted sensor (large signal, fast charge collection) Only small chips possible Back-gate effect (depletion voltage couples to FET gate) C. Mariñas, IFIC, CSIC-UVEG

Double pixel structure C. Mariñas, IFIC, CSIC-UVEG

Gain and noise Ba-133 (30keV -ray) → ADC Units Cd-109 (22keV -ray) → ADC Units E (keV) ADU FIT y=a+ bx Slope=Gain b=12.5 ADC/keV NoiseGainEnergy to create e - h C. Mariñas, IFIC, CSIC-UVEG

S/N for a MIP 1.- ATLAS supposition: 1 MIP → pairs e - h in 285μm of Si 2.- Our DEPFET has 450μm of Si 3.- The scale factor between Ba keV  and a MIP is: 4.- The S/N of 30keV Ba-133  ray scaled to a MIP: C. Mariñas, IFIC, CSIC-UVEG

Noise in current 1.- ADC dynamic range: 2 V – 14 bits -> 2.- trans-impedance amplifier gain = 1 V / 50 A ADC counts of noise C. Mariñas, IFIC, CSIC-UVEG

Introducing the device Switchers A (Gate) and B (Clear) for CLG A-GATEB-CLEAR CURO C. Mariñas, IFIC, CSIC-UVEG

CLG vs CCG V Cleargate-Low V Cleargate-High Amp/mV Time/ms V Clear-High V Clear-Low Clocked- Cleargate V Common-Cleargate V Clear-High V Clear-Low Common- Cleargate C. Mariñas, IFIC, CSIC-UVEG

Effect on spectrum #Entries ADU Signal peak Incomplete clear Noise peak Leackage Current Background C. Mariñas, IFIC, CSIC-UVEG

Amplifiers OUT IN - 5V 1.8V1.3V - 3.2V - 8.2V V substr 39kΩ I in AD8015 AD8129 5V14V +IN -IN REF FB >2V 2kΩ18kΩ 6mV R10 R50 150p F 7V - 7V C. Mariñas, IFIC, CSIC-UVEG

10V C. Mariñas, IFIC, CSIC-UVEG

Double pixel structure Actual size of two pixels Double pixel cell 33 x 47 µm 2 C. Mariñas, IFIC, CSIC-UVEG

V DRAIN V GATE GND 55 Fe Light PulsersSequencer ShaperADC PC C. Mariñas, IFIC, CSIC-UVEG

CDS Correlated Double Sampling Scheme C. Mariñas, IFIC, CSIC-UVEG