Synchron’08 Jean-François LE TALLEC INRIA SOP lab, AOSTE INRIA SOP lab, EPI AOSTE ScaleoChip Company SoC Conception Methodology

2 System on Chip & conception Early experiment & result Next

System on Chip 3 What’s a SoC ? Piece of software IP software for modularity IP software

System on Chip 4 What’s a SoC ? Piece of software & hardware IP software for modularity IP hardware for fast execution IP software IP hardware

System on Chip 5 What’s a SoC ? Piece of software & hardware & interconnect IP software for modularity IP hardware for fast execution interconnect IP software IP hardware

System on Chip 6 What’s a SoC ? Piece of software & hardware & interconnect IP software for modularity IP hardware for fast execution interconnect IP software Chip System IP hardware

SoC conception 7 full design software Spec Final product Usual methodology up to now:

SoC conception 8 full design software Spec FPGA pre-design software ScaleoChip methodology: Real design Final product  Speed up SoC conception  More tolerant to bug Spec Usual methodology up to now:

Designing problems 9 Problems up to now Hardware needed to test software Interconnect Dimensioning HW/SW partitioning

Designing problems 10 Problems up to now Hardware needed to test software Interconnect Dimensioning HW/SW partitioning Potential solution Physical one : ScaleoChip Virtual one : virtual platform ARM SoC designer (SystemC inside) Virtutech Vast Coware Cofluent

SystemC 11 C++ library Aiming to describe HW & SW Different level of description PV to RTL Simulation & event based wait on event or on time Hierarchical description modules, ports, signals Process type sc_method sc_thread

Early experiments 12 Encoding of a realistic case study of an IP component : Proprietary Flash Controller from Verilog to SystemC (our running example) Cortex M3 AHB2APB Bridge Flash Controller Flash A Flash B AHB Bus

Early experiments 13 Several steps replace Verilog version by SystemC-RTL rewritting verify behavior preservation plug in a larger system description for RTL simulation

Early experiments 14 Several steps replace Verilog version by SystemC-RTL rewritting verify behavior preservation plug in a larger system description for RTL simulation Results Time consuming Behavior can be maintained Simulation consumes 11% more than original one

Early experiments 15 Several steps replace Verilog version by SystemC-RTL rewritting verify behavior preservation plug in a larger system description for RTL simulation Results Time consuming Behavior can be maintained Simulation consumes 11% more than original one => Don’t really scale up

Some other results 16 SystemC scheduler Parallelism emulation method re-activation during delta-cycle til stabilization => event partially ordered may be more efficient Assume static cycle will stabilize Known at simulation time if scenario is well chosen

Next 17 Flash Controller control oriented three different interfaces kind of synchronous behavior

Next 18 Flash Controller control oriented three different interfaces kind of synchronous behavior Rise level of description (abstraction) Two options : SystemC-TLM Multi-clock Esterel  Models control part in Esterel  See what could be TLM programming in Esterel

SystemC vs Esterel 19 Event driven + physical time Input / Sensitivity list Wait() Parallelism emulation Can describe different level of abstraction PV to RTL Simulation based approach Activity stabilization (delta cycle) Clock driven + logical time Input / Interface Await() Parallelism Can describe different level of abstraction (maybe …) Esterel multi-clock ? Synthesis based approach Static cycle must be avoided

Q&A | Q&!A 20 Thanks.

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Convert sc_thread into sc_method + clock 24 thread << event loop wait(event) body1 wait(time) body2 end loop method1 << event << ready_to_restart do body1 emit event_start_count end do clock (min_time_resolution) method2 << event_start_count&clock do when event_start_count count time clock period emit event_time_elapsed end do method3 << event_time_elapsed do body2 emit event_time_elapsed end do

SystemC module representation 25 Here state are methods that potentially emit signal when terminating and then activate other methods

I/O esterel language 26 esterel c/c++ SystemC Verilog VHDL FSM Bliff ?

Esterel method representation 27 Each method can be translate by a state running in parallel with the others and waiting on it sensitivity list to emit signal Loop await event1 emit refresh End loop Loop await event2 emit refresh End loop Loop await refresh if cond then emit event3 End loop