Gérard: The Hard Man behind the Soft Core Satnam Singh Microsoft Research, Cambridge UK The University of Birmingham

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multiple independent multi-ported memories fine-grain parallelism and pipelining hard and soft embedded processors

New.bit File mem File DATA2BRAM ELF File # CPU address space 0xFFFFE xFFFFFFFF. ADDRESS_BLOCK dramctlr BUS_BLOCK [0xFFFFF000:0xFFFFFFFF] xrefdes/dramctlr/bram0 [7:0] LOC=RAMB16_X0Y0; xrefdes/dramctlr/bram1 [15:8] LOC=RAMB16_X1Y0; xrefdes/dramctlr/bram2 [23:16] LOC=RAMB16_X2Y0;... END_BUS_BLOCK; END_ADDRESS_BLOCK; BlockRam Memory Map (.bmm) bit File

ZBT SSRAM SDRAM ZBT SSRAM Controller SDRAM Controller 405 PPC On-Chip Peripheral ROM High-Speed Peripheral On-Chip Peripheral CoreConnect OPB (On-Chip Peripheral Bus) OPB DDR SDRAM CoreConnect Processor Local Bus (PLB) Arbiter DDR SDRAM Controller External Bus Controller OPB Bridge I-Cache PLB D-Cache PLB

locks monitors condition variables spin locks priority inversion

PLDI 1998

PLDI 1999

PLDI 2000

POPL 1998

POPL 1999

POPL 2000

ray of light Signal Lustre PRET-C SHIM Jazz Esterel

San Jose, 6 June 2003

Sylvan Dissoubray

Gérard wearing Satnam’s ring Satnam wearing Gérard’s ring San Jose, 6 June 2003

Gérard Berry Synchronous Programming Language Combat Team Albert Benveniste Nicolas Halbwachs

Zero delay example: Newtonian Mechanics Concurrency + Determinism Calculations are feasible

Predictable delay examples: sound, light, waves Wait long enough, same result as 0-delay ! Zero delay and predictable delay are fully compatible Constructive semantics is the unification A theory of causality for reactive systems Clocked digital circuits paradigm

Safe State Machines Esterel code loop [ await A || await B ] ; emit O each R

Esterel design void uart_device_driver () {..... } uart.c VHDL, Verilog -> hardware implementation C -> software implementation

Hardware UART

Software UART

18/01/ G. Berry, Microsoft Research Project Structure Automatic Documentation Project Management Executable Specification Exporter Debugging & Simulation Formal Verification Design Verification Sequential Equivalence check DUT  Optimized for synthesis DFT-ready SystemC & RTL flow integration C / C++ / SystemCVerilog / VHDL.sc.vhd Architecture Design Specification Capture Design Functional Spec Verification Requirements Architecture Diagram (2007) Editor Simulator Design Verifier Model Reporter Code & Testbench Generators Editor Sequential Equivalence Checker IDE Player IDE

18/01/ G. Berry, Microsoft Research SCADE in the Airbus A380 –Flight Control system –Flight Warning system –Electrical Load Management system –Anti Icing system –Braking and Steering system –Cockpit Display system –Part of ATSU (Board / Ground comms) –FADEC (Engine Control) –EIS2 : Specification GUI Cockpit: –PFD : Primary Flight Display –ND : Navigation Display –EWD : Engine Warning Display –SD : System Display Flight Control Primary & Secondary Commands Anti Ice Control Unit Flight Warning System Braking & Steering Control Unit

French Synchronous Language Thread Level Remains High SEVERE: hysteresis HIGH: deadlock ELEVATED: priority inversion GUARDED: non-atomic action LOW: race condition

begin … end procedure static final void for while loop accept if then else case

present gift then await scream end present Thank you Stephen Edwards

present gift then pause; every day do await thanks end every end present Thank you Stephen Edwards

abort nothing when bored Thank you Stephen Edwards

every day do nothing end every Thank you Stephen Edwards

run slowly Thank you Stephen Edwards

await falls ; every body do sustain disbelief end every Thank you Stephen Edwards

present case legally do run away end present Thank you Stephen Edwards

abort task when immediate objection Thank you Jens Brandt

abort run slowly || run fastly when sleepy Thank you Mike Kishinevsky

trap mouse in every loop do run cheese end every handle hair do run water end trap Thank you Mike Kishinevsky

Engine control software programmed in Esterel by non-French speaker

Kavi Arya, Mumbai, 10 January 2004

Esterel present A then emit A end

QEsterel present A then emit A end Thank you Georges Gonthier

Mike Kishinevsky