Advanced Digital Design The Synchronous Design Paradigm A. Steininger Vienna University of Technology

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 2 Outline The Need for a Design Style The Need for a Design Style The „ideal“ Method – Requirements The „ideal“ Method – Requirements The Fundamental Problem The Fundamental Problem Timed Communication Model Timed Communication Model Synchronous Design as a Solution Synchronous Design as a Solution Pros & Cons of Synchronous Design Pros & Cons of Synchronous Design

Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 3 Why a Design Stlye? Skew is inevitable and unpredictable Skew is inevitable and unpredictable It causes inconsistent transient states It causes inconsistent transient states Their logic evaluation causes glitches Their logic evaluation causes glitches Boolean Logic forms a digital abstraction, as- suming continuous signal validity & consistency Boolean Logic forms a digital abstraction, as- suming continuous signal validity & consistency In addition, we need a design style to maintain these abstractions in the presence of skew In addition, we need a design style to maintain these abstractions in the presence of skew recall

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 4 Without a Design Style… …combinational gates may, due to race conditions, receive contradictory inputs „simultaneously“, hence …combinational gates may, due to race conditions, receive contradictory inputs „simultaneously“, hence create glitch or runt pulses that may create glitch or runt pulses that may be converted into erroneous stable states or be converted into erroneous stable states or even cause metastability in storage loops. even cause metastability in storage loops. These glitches, runts and/or manifestations of metastability may propagate, and These glitches, runts and/or manifestations of metastability may propagate, and they may be subject to „Byzantine“ inter- pretation, causing further erroneous states. they may be subject to „Byzantine“ inter- pretation, causing further erroneous states. recall

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 5 The Chip Design Crisis designer productivity gap hard physical limits impede miniaturization excessive test complexity heat problems power delivery problems increasing transient fault rates hard physical limits impede speed-up increasing NRE costs short time-to-market Do we need a new („revolutionary“) design approach?

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 6 A Fair Comparison Severe technological problems force us to question the synchronous design practice. Severe technological problems force us to question the synchronous design practice. Alternatives must be critically evaluated with respect to improvements concerning Alternatives must be critically evaluated with respect to improvements concerning area („embedded“, „intelligent“, cost…) area („embedded“, „intelligent“, cost…) power (mobile devices, heat,…) power (mobile devices, heat,…) performance (as always) performance (as always) designability (efficient design of complex sys.) designability (efficient design of complex sys.) verifiability (test & validation cost!) verifiability (test & validation cost!) robustness (critical apps, higher fault rates,…) robustness (critical apps, higher fault rates,…)

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 7 Performance Performance has been improved by Transistor scaling (technology) Transistor scaling (technology) Architectrural advances (pipelines, caches, prediction,…) Architectrural advances (pipelines, caches, prediction,…) Parallelization (vector operations, multicore,…) Parallelization (vector operations, multicore,…)  The design style has remained unchanged !

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 8 Verification Need to make sure that implemen- tation matches specification: Need to make sure that implemen- tation matches specification: all desired functions available all desired functions available no undesired behavior no undesired behavior 70% of time spent on verification 70% of time spent on verification Model-based approach: Model-based approach: spec transformed into (high-level) model spec transformed into (high-level) model model properties formally verified model properties formally verified model is implemented in HW & SW model is implemented in HW & SW BUT: how check implementation vs. model??

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 9 Test Test complexity rises with more than O(n 2 ) with circuit complecity Test complexity rises with more than O(n 2 ) with circuit complecity It will soon cost more to test a transistor than to manufacture it It will soon cost more to test a transistor than to manufacture it log € cost/trans test costs -29%/a  const [ITRS] t

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 10 Transient Faults …occur 10…100 times more often than permanent faults today …occur 10…100 times more often than permanent faults today …originate from storage elements being upset (directly or indirectly) …originate from storage elements being upset (directly or indirectly) …can only be caused by disturbances with an energy larger than that stored in the affected cell …can only be caused by disturbances with an energy larger than that stored in the affected cell … are often caused by particle hits (single event upsets: SEUs) … are often caused by particle hits (single event upsets: SEUs)

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 11 Fault Rate Predictions energy stored in a storage element scales with energy stored in a storage element scales with feature size feature size power supply power supply energy distribution of particles is non-linear energy distribution of particles is non-linear significantly more particles towards lower energy significantly more particles towards lower energy fault potential largely increases with every technology node

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 12 Fault Mitigation stopping miniaturization stopping miniaturization is not an option is not an option technology (materials, shielding,…) technology (materials, shielding,…) reduces fault rate per transistor reduces fault rate per transistor but still overall increase per chip but still overall increase per chip robust circuit design robust circuit design Several techniques applied, but Several techniques applied, but Design style not changed Design style not changed system-level fault tolerance system-level fault tolerance current solution, expensive (typ. 3x) current solution, expensive (typ. 3x)

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 13 A First Summary An ideal design method … minimizes power consumption minimizes power consumption miminizes area overhead miminizes area overhead naturally supports intuitive design naturally supports intuitive design naturally aids testability naturally aids testability yields robust circuits yields robust circuits yields fast circuits. yields fast circuits.

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 14 Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 15 What we actually need SRCSNK f(x) When it is valid and consistent When SNK has consumed the previous one When can SNK use its input? When can SRC apply the next input? completion detection problem input/output mode operation, requires indication principle

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 16 Timed Comm. Model for details see: M. Delvai, A. Steininger. Solving the fundamental Problem of Digital Design – A Systematic Review of Design Methods, 9th Euromicro Conference on System Design, Dubrovnik „contamination delay“

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 17 The Capture Condition Control TRGSNK: Have SNK capture data only after it has become consistent. Formal Condition: t cons,x > t snkrdy,x  snk > -  snktrg

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 18 The Issue Condition Control TRGSRC: Have SRC issue the next data word such that the current one can still be safely consumed by SNK. Formal Condition: t invalid,x > t safe,x  src > -  invalid

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 19 Our Options We must only use consistent input vectors We must only use consistent input vectors How can we tell an input vector is consistent? How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base synchronous approach / global time base asynchronous/bounded delay asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive asynchronous/delay insensitive

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 20 Control by Global Time

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 21 The Synchronous Concept f(x) FF1FF2 T Clk periodic Pure time domain solution: use periodic clock edges to derive triggers for SRC & SNK; determine period such that capture condition and issue condition are always fulfilled.

Synchr. Timing Model How does the synchronous design fit into the timing model of global time? How does the synchronous design fit into the timing model of global time? What is  ? What is  ? What is  ? What is  ? Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 22

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 23 The Implications Clock Period T Clk = Period  Clock Period T Clk = Period  determined by static timing analysis determined by static timing analysis Free choice of  snk :  capture condition Free choice of  snk :  capture condition Phase  =  (!) Phase  =  (!) this implies that this implies that  src = -( snktrg +  cons ) still we must guarantee still we must guarantee  src > - invalid (issue condition) Therefore it must hold that Therefore it must hold that  invalid >  snktrg +  cons This is not formally safe – but it works! (No freedom to choose!)

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 24 Benefits of Sync. Logic Simplicity improves productivity Simplicity improves productivity time is considered discrete (!) time is considered discrete (!) design on high level of abstraction design on high level of abstraction transients are irrelevant, all considered states are clearly defined transients are irrelevant, all considered states are clearly defined timing analysis separate, after design timing analysis separate, after design clear distinction between data & clock clear distinction between data & clock

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 25 Benefits of Sync. Logic (2) High implementation efficiency: High implementation efficiency: one single control signal for the complete system! one single control signal for the complete system! periodic clock is easy to generate periodic clock is easy to generate single-rail data coding single-rail data coding minimum number of transitions on the data rails minimum number of transitions on the data rails clock also provides a time base clock also provides a time base

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 26 Resume 1 Synchronous design does work Synchronous design does work billions of working designs billions of working designs Synchronous design is VERY efficient Synchronous design is VERY efficient wrt. design (intuition) wrt. design (intuition) wrt. implementation (area) wrt. implementation (area) So everything is solved So everything is solved Is it? Is it?

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 27 The Original Problem SRCSNK f(x) When it is valid and consistent When SNK has consumed the previous one When can SNK use its input? When can SRC apply the next input? recall

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 28 What have we done? We have expressed a simple information related condition by means of complicated timing related parameters that we don‘t even know! DOES IT MATTER ? recall

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 29 That damned traffic light YES! It does matter

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 30 That damned … Traffic light Traffic light number of waiting cars number of waiting cars Microwave oven Microwave oven temperature of the food temperature of the food Wiper Wiper visibility through the front shield visibility through the front shield Stairway light Stairway light presence of a person in the stairway presence of a person in the stairway

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 31 What‘s wrong? As time is easy to measure, a projection is often made for the relative time between the occurrence of an event in the past and one expected in the future – instead of directly observing the latter. As time is easy to measure, a projection is often made for the relative time between the occurrence of an event in the past and one expected in the future – instead of directly observing the latter. This requires a model to be established, expressing how the quantity of interest relates to time. This requires a model to be established, expressing how the quantity of interest relates to time. This becomes annoying when this artificial relation between actual event and time is so weak that either the model prediction gets too fuzzy, or the model too complicated. This becomes annoying when this artificial relation between actual event and time is so weak that either the model prediction gets too fuzzy, or the model too complicated.

Pre-Determined Timing Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 32 Designer system model projected conditions User actual conditions actual system worst case safety margins ?(unknown) ?(imperfections) Timing completely fixed after design No way to react to actual conditions & system

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 33 The Synchronous Approach f(x) FF1FF2 T Clk „After some TIME T clk FF2 can use f(x)‘s output and at the same time FF1 can apply a new input“ Relating flow control to time in this way is convenient and effective, but in fact the implied relation does not (naturally) exist! We need to establish this relation artificially during design (timing optimization & constraints) and preserve it during operation (temp, VCC) => „contract“ between designer, fab and user

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 34 The annoying consequences need to determine clock period need to determine clock period circuit functionality is technology dependent circuit functionality is technology dependent substantial design efforts, large design loops substantial design efforts, large design loops need to make worst-case assumptions need to make worst-case assumptions necessarily pessimistic (corner cases) necessarily pessimistic (corner cases) still no robustness wrt. exceeding them still no robustness wrt. exceeding them need to maintain global synchrony need to maintain global synchrony clock distribution problems (skew!) clock distribution problems (skew!) power consumption problems power consumption problems

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 35 Timing Analysis not possible before the end of the design flow (large iteration loops!) not possible before the end of the design flow (large iteration loops!) Design-Entry Synth. & Technol.-Mapping Partitioning & Placement Routing Manufact. Specification Operation gate delays interconnect delays P-variations VT-variations

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 36 normally too pessimistic normally too pessimistic real, chip could run faster no tolerance when exceeded no tolerance when exceeded graceful degradation desirable    lim Worst-Case Assumptions

The Clock Skew Problem What happens if we move SRC time against SNK time? What happens if we move SRC time against SNK time? Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 37

Sync. Design – Properties Area: + single rail encoding, single clock line - clock network Area: + single rail encoding, single clock line - clock network Power: + small, efficient circuit - clock net, permanent concurrent switching Power: + small, efficient circuit - clock net, permanent concurrent switching Performance: + pure feed-forward flow control - worst case design, safety margins Performance: + pure feed-forward flow control - worst case design, safety margins Designability: + good abstraction level for logic - timing analysis complex, composability? Designability: + good abstraction level for logic - timing analysis complex, composability? Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 38

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 39 Robustness  metastability Issues  clock = single point of failure  non-redundant signal coding  no graceful degradation timing margins help masking faults timing margins help masking faults  but they are shrinking!  synchrony is a very strong assumption  it takes a lot of efforts to maintain it  „assumption coverage“ is lower

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 40 Experimental Results Fault Injection Results for SPEAR [Thesis Rahbaran] PhD Huber: Design Flow & Validation asyn SPEAR PhD Delvai: Design asynchronous processor SPEAR PhD Rahbaran: Robustness Comparison syn/asyn

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 41 Fault Masking Effects electrical masking electrical masking too short fault pulse is filtered out by (parasitic) low-passes too short fault pulse is filtered out by (parasitic) low-passes logical masking logical masking faults on masked gate inputs are irrelevant faults on masked gate inputs are irrelevant temporal masking temporal masking signal values are considered only shortly before/during latching window; faults go unrecognized when outside signal values are considered only shortly before/during latching window; faults go unrecognized when outside 0 0 Diploma thesis: Fault masking syn vs. asyn

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 42 Scan test turns sequential problem into combinational one => hard to beat! Testability

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 43 Conclusion An analysis of the data transfer process allows mapping the trigger conditions for data source and sink to the time domain, yielding an „issue condition“ and a „capture condition“. An analysis of the data transfer process allows mapping the trigger conditions for data source and sink to the time domain, yielding an „issue condition“ and a „capture condition“. A convenient mapping to a purely time based solution is used by some design styles, in particular the synchronous design. A convenient mapping to a purely time based solution is used by some design styles, in particular the synchronous design. This mapping is, however, not natural. This mapping is, however, not natural. As an alternative signal coding may be used to control the triggers of source and sink. As an alternative signal coding may be used to control the triggers of source and sink.

Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 44 Conclusion Synchronous design is extremely efficient wrt. design and testing. Synchronous design is extremely efficient wrt. design and testing. It builds on a relation between handshake events and time that becomes increasingly cumbersome. It builds on a relation between handshake events and time that becomes increasingly cumbersome. Weak points are inherent robustness and composability Weak points are inherent robustness and composability Power efficiency, area efficiency and performance efficiency are very good in principle, but limitations in clock distributions tend to foil these benefits. Power efficiency, area efficiency and performance efficiency are very good in principle, but limitations in clock distributions tend to foil these benefits.