Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei ECE 300 Advanced VLSI Design Fall 2006 Lecture 24: CAD Systems & Algorithms Yunsi Fei [Adapted from Jan Rabaey et al’s Digital Integrated Circuits ©2002, PSU Irwin & Vijay © 2002, and Princeton Wayne Wolf’s Modern VLSI Design © 2002 ]

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Topics CAD systems and algorithms (§10) –CAD systems (§10.2) –Hardware-software co-design (§10.11) –High-level synthesis (§10.10) –State optimizations (§10.9)

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei CAD systems n Too many transistors, too little time! – have to resort to CAD tools when design IC with billions of transistors n Tools aren’t very useful unless they talk to each other. n Design interchange languages: –VHDL (TM), Verilog (TM) (function and structure); –EDIF (netlists); –GDS, CIF (masks).

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei CAD tool interactions database tool 1tool 2 tool 3tool 4 database (hub-and-spoke)translator tool 1tool 2 tool 3tool 4 xlate a xlate c xlate b xlate e xlate d

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Back annotation n Often want to iteratively improve design. n Back annotation updates a more-abstract design with information from later design stages. –Example: annotate logic schematic with extracted parasitic Rs and Cs. n Back annotation requires tools to know more about each other.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei An Automated Design Flow High-level synthesis Logic Synthesis Technology Mapping Placement and Routing High level description (VHDL, Verilog) RT-level description (VHDL, Verilog) Netlist (EDIF format) Layout(GDSII, CIF format)

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Verification and testing n Errors could be introduced at different stages –At design stage –At fabrication stage n How do we guarantee our design is correct? –Verification –e.g. Simulation, model checking n How do we know if the chip is functioning? –Testing

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Event-driven simulation n Event-driven simulation is designed for digital circuit characteristics –small number of signal values; –relatively sparse activity over time. n Event-driven simulators try to update only those signals which change in order to reduce CPU time requirements.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Event-driven simulator structure n An event is a change in a signal value. n A timewheel is a queue of events. n Simulator traces structure of circuit to determine causality of events—event at input of one gate may cause new event at gate’s output.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Event-driven simulation example A B C D logic networkbehavior

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Event-driven simulation example, cont’d n Events at primary inputs: –A changes at t=1; –B changes at t=2. n Immediate causality: –C changes at t=3 when both inputs to NOR are 0. n Event propagation: –D changes at t=4.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Delay models n Unit-delay simulators assume that each component has a one-unit delay. Model function but not performance. n Variable-delay simulators allow each component to have its own delay. Accuracy of performance estimates from variable- delay simulators depends on how well circuits can be extracted to digital model.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Switch simulation n Special type of event-driven simulation optimized for MOS transistors. n Treats transistor as switch. Takes capacitance into account to model charge sharing, etc. n Can also be enhanced to model transistor as resistive switch.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Switch simulation example

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Switch simulation example, cont’d n Node g may be connected to either power supply, but signals on that node are terminated by gate of transistor. n To solve for values of a and b nodes, must first solve for value of g node. –If g=1, then a=b. –If g=0, other parts of circuit determine a and b independently.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Switch simulation and charge sharing n Closed transistor connects source and drain nodes. Want to determine voltages of source/drain nodes taking into account capacitance. n Capacitance determines node size. Use size of connected nodes to determine new value of nodes. n Result may be X (unknown).

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Topics n CAD systems and algorithms (§10) –CAD systems (§10.2) –Hardware-software co-design (§10.11) –High-level synthesis (§10.10) –State optimizations (§10.9)

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Hardware/software co-design n Use programmable CPUs along with specialized logic blocks to implement a particular application. n CPUs can implement background functions much more efficiently than dedicated logic: higher utilization of logic. n Important in systems-on-chip.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Co-synthesis styles n Hardware/software partitioning: –Architectural template consists of 1 CPU + n ASICs. –Put operations on CPU or ASIC. n Distributed system synthesis: –No fixed architectural template. –Allocate function units and communication, schedule operations.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Topics n CAD systems and algorithms (§10) –CAD systems (§10.2) –Hardware-software co-design (§10.11) –High-level synthesis (§10.10) –State optimizations (§10.9)

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei High-Level Synthesis n High-level synthesis systems translate behavioral descriptions into register-transfer implementations by scheduling and binding, and control optimization. n Most high-level synthesis systems concentrate on data paths.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Force-directed scheduling n Compute schedulable range of each operator by computing ASAP, ALAP schedules –Find a schedule that involves lowest cost between ASAP and ALAP Distribution cost = cost of operator  probability it will be scheduled in that step. n Force = difference between distribution cost at a control step and average distribution.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Example n Cost distribution –Assume adder cost 1 –2, 2.5, 1.5 for stage 1, 2, 3 n Force calculation –For each possible move »F A=1 = (2-2.5)×.5 = -.25 »F B=1 = (2-2.5)×.5 = -.25 »F B=2 =F C=3 = (2-2.5)×.5 = -.25 »F C=2 = ( )×.5 = 0.5 –Take the smallest force ASAPALAP A C B

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Example

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Scheduling under resource constraints ASAP Resource constraints

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Scheduling extensions n Chaining: executing several operators in one cycle to balance path lengths. n Multicycling: executing a pipelined operator over several cycles.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Binding n Which resource(s) should be used for a specific operation, and which storage element used for a variable n Datapath element allocation –Straightforward n Register allocation for variables –Can be formulated as clique partitioning. –Good heuristic algorithms exist to solve clique partitioning problems

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Clique partitioning n Resource allocation graph –Node: an element to be allocated. –Edge: Two elements can share the resource n Clique: A fully-connected subgraph n Example –Two variables can share the same register if they are not live at any given time

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Clique partitioning example A C E B D F

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Resource binding on a scheduled graph

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Topics n CAD systems and algorithms (§10) –CAD systems (§10.2) –Hardware-software co-design (§10.11) –High-level synthesis (§10.10) –State optimizations (§10.9)

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Sequential machine optimizations n State assignment: choose codes for states. n Create common factors in states by assigning them close codes: –s0 = 000, s1 = 001 (x 0 ’ x 1 ’ x 2 ); –s0 + s1 = x 0 ’ x 1 ’. n If all constraints cannot be satisfied in minimum number of bits, can add bits to code to allow constraints to be satisfied

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei Adding code bits code groups: s1, s2 s2, s3 s3, s4 S1S1 S2S2 S3S3 S4S4