23 October 2003Matthew Warren - Trigger Module Update - RAL1 CALICE CIRC BE-FPGA Trigger Module Update Matthew Warren University College London 23 October 2003

Matthew Warren - Trigger Module Update - RAL2 Progress Code continues to grow - Trying to finalise a structure for the BE-FPGA Looking at BE-FPGA pin-out control - Suggest single list, web accessible. Setting up structures for CVS - Directory tree/.cvsignores - Stand alone components Looking at a test system configuration - External trigger generator (via back-plane) - Full Read/Write Trig Test Interface (more later)

23 October 2003Matthew Warren - Trigger Module Update - RAL3 Trigger Inteface Test System Called TrigITS! Built on Dev-Board Stand-alone Real Trigger code testing - LVDSOUT to LVDSIN Connect to backplane via test connector. Register access via RS232 RS232 level translation for other modules

23 October 2003Matthew Warren - Trigger Module Update - RAL4 CALICE OctNovDecJan Trigger Interface Test System Trigger Pass-through Internal/Stand Alone Funcs Main Functions VME Access Header Data Testing ZEUS, ATLAS, Holiday Schedule