Moon-Su Kim, Sunik Heo, DalHee Lee, DaeJoon Hyun, Byung Su Kim, Bonghyun Lee, Chul Rim, Hyosig Won, Keesup Kim Samsung Electronics Co., Ltd. System LSI.

Slides:



Advertisements
Similar presentations
Design and Implementation of VLSI Systems (EN1600)
Advertisements

Logic Gate Delay Modeling -1 Bishnu Prasad Das Research Scholar CEDT, IISc, Bangalore
Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao.
Topics Electrical properties of static combinational gates:
EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department.
Advanced Interconnect Optimizations. Buffers Improve Slack RAT = 300 Delay = 350 Slack = -50 RAT = 700 Delay = 600 Slack = 100 RAT = 300 Delay = 250 Slack.
ELEN 468 Lecture 261 ELEN 468 Advanced Logic Design Lecture 26 Interconnect Timing Optimization.
Timing Margin Recovery With Flexible Flip-Flop Timing Model
Lecture 5: DC & Transient Response
Chop-SPICE: An Efficient SPICE Simulation Technique For Buffered RC Trees Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov Dept. of EECS, University of.
The Cost of Fixing Hold Time Violations in Sub-threshold Circuits Yanqing Zhang, Benton Calhoun University of Virginia Motivation and Background Power.
NuCAD ELECTRICAL ENGINEERING AND COMPUTER SCIENCE McCormick Northwestern University Robert R. McCormick School of Engineering and Applied Science FA-STAC.
EE4271 VLSI Design Interconnect Optimizations Buffer Insertion.
Statistical Crosstalk Aggressor Alignment Aware Interconnect Delay Calculation Supported by NSF & MARCO GSRC Andrew B. Kahng, Bao Liu, Xu Xu UC San Diego.
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response
04/11/02EECS 3121 Lecture 26: Interconnect Modeling, continued EECS 312 Reading: 8.2.2, (text) HW 8 is due now!
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 11: Logical Effort (1/2) Prof. Sherief Reda Division of Engineering, Brown.
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.
Constructing Current-Based Gate Models Based on Existing Timing Library Andrew Kahng, Bao Liu, Xu Xu UC San Diego
04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)
Interconnect Optimizations
Chung-Kuan Cheng†, Andrew B. Kahng†‡,
On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.
1 UCSD VLSI CAD Laboratory ISQED-2009 Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization Kwangok Jeong, Andrew.
Outline Noise Margins Transient Analysis Delay Estimation
NuCAD ELECTRICAL ENGINEERING AND COMPUTER SCIENCE McCormick Northwestern University Robert R. McCormick School of Engineering and Applied Science Nostra-XTalk.
DC and transient responses Lezione 3
CMOS VLSI Design4: DC and Transient ResponseSlide 1 EE466: VLSI Design Lecture 05: DC and transient response – CMOS Inverters.
Statistical Gate Delay Calculation with Crosstalk Alignment Consideration Andrew B. Kahng, Bao Liu, Xu Xu UC San Diego
EE4800 CMOS Digital IC Design & Analysis
EE 447 VLSI Design 4: DC and Transient Response1 VLSI Design DC & Transient Response.
Advanced Interconnect Optimizations. Timing Driven Buffering Problem Formulation Given –A Steiner tree –RAT at each sink –A buffer type –RC parameters.
Noise and Delay Uncertainty Studies for Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu † and Devendra Vidhani ‡ UCLA Computer Science Department,
The CMOS Inverter Slides adapted from:
Signal Integrity Methodology on 300 MHz SoC using ALF libraries and tools Wolfgang Roethig, Ramakrishna Nibhanupudi, Arun Balakrishnan, Gopal Dandu Steven.
Practical Aspects of Logic Gates COE 202 Digital Logic Design Dr. Aiman El-Maleh College of Computer Sciences and Engineering King Fahd University of Petroleum.
MOS Inverter: Static Characteristics
Andrew B. Kahng‡†, Mulong Luo†, Siddhartha Nath†
Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera Kyoto University.
A comparison between different logic synthesis techniques from the digital switching noise viewpoint G. Boselli, V. Ciriani, V. Liberali G. Trucco Dept.
EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Static Timing Analysis and Gate Sizing.
Chapter 07 Electronic Analysis of CMOS Logic Gates
Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics;
EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Interconnect Jan M. Rabaey Anantha Chandrakasan Borivoje.
Logical Effort and Transistor Sizing Digital designs are usually expected to operate at high frequencies, thus designers often have to choose the fastest.
Introduction to CMOS VLSI Design Lecture 5: Logical Effort GRECO-CIn-UFPE Harvey Mudd College Spring 2004.
Linear Delay Model In general the propagation delay of a gate can be written as: d = f + p –p is the delay due to intrinsic capacitance. –f is the effort.
Introduction to CMOS VLSI Design MOS devices: static and dynamic behavior.
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Circuit design for FPGAs n Static CMOS gate vs. LUT n LE output drivers n Interconnect.
Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect. n Switch logic.
FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Topics n Logic gate delay. n Logic gate power consumption. n Driving large loads.
Analog to Digital Converters
UC San Diego / VLSI CAD Laboratory Learning-Based Approximation of Interconnect Delay and Slew Modeling in Signoff Timing Tools Andrew B. Kahng, Seokhyeong.
Chapter 6 Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. High-Speed CMOS Logic Design.
Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect.
Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics;
Static Timing Analysis
-1- Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products Samyoung Bang #, Kwangsoo Han ‡, Andrew B.
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits Yehea I. Ismail and Eby G. Friedman, Fellow, IEEE.
1 Modeling and Optimization of VLSI Interconnect Lecture 2: Interconnect Delay Modeling Avinoam Kolodny Konstantin Moiseev.
COE 360 Principles of VLSI Design Delay. 2 Definitions.
CMOS VLSI Design Lecture 4: DC & Transient Response Younglok Kim Sogang University Fall 2006.
Motivation Process & Design trends
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
SIDDAGANGA INSTITUTE OF TECHNOLOGY
DC & Transient Response
Lecture 5: DC & Transient Response
Submitted by HARSHITHA G H
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Presentation transcript:

Moon-Su Kim, Sunik Heo, DalHee Lee, DaeJoon Hyun, Byung Su Kim, Bonghyun Lee, Chul Rim, Hyosig Won, Keesup Kim Samsung Electronics Co., Ltd. System LSI Division

Dr. Cho Moon Dr. Peter Kim PrimeTime Group(Amrita, JW Jang) SiliconSmart Group(Moninder, JH Song) 1

Introduction Background Library Characterization Waveform Waveform Propagation Using Library Noise Model Experimental Results Runtime Impact Conclusion 2

Impact of Scaling Wire resistance is linearly increased according to process nodes -Long tail due to wire resistance No significant change in wire capacitance -Device pin cap has relatively larger impact on delay -Accurate analysis of Miller effect between input and output pin is more important 3

Conventional timing analysis with non-linear delay model (NLDM) NLDM cannot consider Miller effect and long tail effect Timing analysis results can be more optimistic than SPICE results Composite current source (CCS) model results are similar to NLDM results 4 Strong miller effect Long tail effect Drive Strength

Long tail effect Slew degradation by wire resistance  long tail Same input transition(30% ~ 70%)  different propagation delay : long tail effect 5 model) next A(real) next A(driver model) waveform at end of wire waveform at driver output Inputoutput Delay difference due to tail of waveform

Miller effect Impact on current stage delay -Large receivers that are lightly loaded can inject a bump back to the interconnect through the Miller cap (similar to crosstalk) -Receiver acts as an aggressor driver even though there is no external crosstalk source. Impact on output waveform -Waveform is too distorted to be modeled by any pre-driver accurately -Distortion is instance specific and cannot be modeled by characterization -Representing this complex waveform with delay and slew is not accurate 6

Goal is to drive library cells with waveforms that approximate real waveforms Need to consider both fast input slew with no RC network effect and slow input slew with significant RC network effect Can control waveform shape by varying weights of linear ramp vs. exponential component V_pre-driver = V_linear * ratio + V_exponential *(1-ratio) Can consider slew degradation at wire by using the lower ratio (more exponential component) Pre-driver ratio (PDR) of 0.3 means 30% linear and 70% exponential 7

Library noise model is required Library was characterized using a pre-driver waveform generated from a mixture of linear ramp and exponential waveform Waveform propagation method Enable propagation of waveforms for both clock and data networks CCS-Noise  gate level simulation  accurate waveform propagation & accuracy improvement on the delay and slew Noise Model Vi Miller Cap Timing Model + Accurate Waveform Propagation + Improved Path Delay & Slew Accuracy Accurate Waveform Propagation + Improved Path Delay & Slew Accuracy =

How well STA consider waveform distortion 9 SPICE Waveform ResultsStatic Timing Analysis Waveform Results

Samsung structural test cases 415 test cases with 14nm technology Inverter / Buffer chains with various fanouts, parasitic loading, and driving strengths Static timing analysis results using library noise model Waveform propagation analysis is enabled for graph-based analysis (GBA) and path-based analysis (PBA) Path delay comparison with SPICE 10 Accuracy significantly improved with waveform propagation NLDMwaveform propagation PDR 0.5PDR 0.3 PDR 0.5PDR 0.3 GBAPBAGBAPBA average-6.0%-1.8%-4.8%-2.2%-2.1%-1.6% stdev7.5%6.4%4.5%1.5%4.3%1.5%

Comparison was made between two models: Old but very fast model (NLDM) New and most accurate model (waveform propagation) On a real 60 M instance design, waveform propagation was 14% slower than NLDM Waveform propagation was enabled for both clock and data networks Runtime increase is tolerable for improved accuracy 11 NLDM (min) Waveform Propagation (min) read_db update_timing PBA (max paths) Total TAT Ratio

Studied waveform distortion due to long tail and miller effect Libraries were characterized using SiliconSmart Timing analysis was performed using PrimeTime SPICE results were obtained using HSPICE For accurate static timing analysis Pre-driver waveform with ratio 0.3 (30% linear ramp and 70% exponential) provided the best accuracy for a slow corner library Accuracy significantly improved with waveform propagation Runtime degradation by waveform propagation is acceptable(14%) 12