Slide-1 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Benchmarking Working Group Session Agenda 1:00-1:15David KoesterWhat Makes HPC Applications Challenging? 1:15-1:30Piotr LuszczekHPCchallenge Challenges 1:30-1:45Fred TracyAlgorithm Comparisons of Application Benchmarks 1:45-2:00Henry NewmanI/O Challenges 2:00-2:15Phil ColellaThe Seven Dwarfs 2:15-2:30Glenn LueckeRun-Time Error Detection Benchmark 2:30-3:00Break 3:00-3:15Bill MannSSCA #1 Draft Specification 3:15-3:30Theresa MeuseSSCA #6 Draft Specification 3:30-??Discussions — User Needs HPCS Vendor Needs for the MS4 Review HPCS Vendor Needs for the MS5 Review HPCS Productivity Team Working Groups

Slide-2 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory This work is sponsored by the Department of Defense under Army Contract W15P7T-05-C-D001. Opinions, interpretations, conclusions, and recommendations are those of the author and are not necessarily endorsed by the United States Government. What Makes HPC Applications Challenging? David Koester, Ph.D January 2005 HPCS Productivity Team Meeting Marina Del Rey, CA

Slide-3 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Outline HPCS Benchmark Spectrum What Makes HPC Applications Challenging? –Memory access patterns/locality –Processor characteristics –Concurrency –I/O characteristics –What new challenges will arise from Petascale/s+ applications? Bottleneckology –Amdahl’s Law –Example: Random Stride Memory Access Summary

Slide-4 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory HPCS Benchmark Spectrum

Slide-5 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory HPCS Benchmark Spectrum What Makes HPC Applications Challenging? Full applications may be challenging due to –Killer Kernels –Global data layouts –Input/Output Killer Kernels are challenging because of many things that link directly to architecture Identify bottlenecks by mapping applications to architectures

Slide-6 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory What Makes HPC Applications Challenging? Memory access patterns/locality –Spatial and Temporal  Indirect addressing  Data dependencies Processor characteristics –Processor throughput (Instructions per cycle)  Low arithmetic density  Floating point versus integer –Special features  GF(2) math  Popcount  Integer division Concurrency –Ubiquitous for Petascale/s –Load balance I/O characteristics –Bandwidth –Latency –File access patterns –File generation rates Killer Kernels Global Data Layouts Killer Kernels Global Data Layouts Input/Output

Slide-7 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Cray “Parallel Performance Killer” Kernels KernelPerformance Characteristic RandomAccessHigh demand on remote memory No locality 3D FFTNon-unit strides High bandwidth demand Sparse matrix-vector multiplyIrregular, unpredictable locality Adaptive mesh refinementDynamic data distribution; dynamic parallelism Multi-frontal methodMultiple levels of parallelism Sparse incomplete factorizationAmdahl’s Law bottlenecks Preconditioned domain decomposition Frequent large messages Triangular solverFrequent small messages; poor ratio of computation to communication Branch-and-bound algorithmFrequent broadcast synchronization

Slide-8 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Killer Kernels Phil Colella —The Seven Dwarfs

Slide-9 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Mission Partner Applications How do mission partner applications relate to HPCS spatial/temporal view of memory? –Kernels? –Full applications? How do mission partner applications relate to HPCS spatial/temporal view of memory? –Kernels? –Full applications? HPCS Challenge Points HPCchallenge Benchmarks Memory Access Patterns/Locality

Slide-10 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Processor Characteristics Special Features Comparison of similar speed MIPS processors with and without –GF(2) math –Popcount Similar or better performance reported using Alpha processors (Jack Collins (NCIFCRF)) Codes –Cray-supplied library –The Portable Cray Bioinformatics Library by ARSC References – – Algorithmic speedup of 120x

Slide-11 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Concurrency Insert Cluttered VAMPIR Plot here

Slide-12 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory I/O Relative Data Latency ‡ Note: 11 orders of magnitude relative differences! ‡ Henry Newman (Instrumental)

Slide-13 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory I/O Relative Data Bandwidth per CPU ‡ Note: 5 orders of magnitude relative differences! ‡ Henry Newman (Instrumental)

Slide-14 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Strawman HPCS I/O Goals/Challenges 1 Trillion files in a single file system –32K file creates per second 10K metadata operations per second –Needed for Checkpoint/Restart files Streaming I/O at 30 GB/sec full duplex –Needed for data capture Support for 30K nodes –Future file system need low latency communication An envelope on HPCS Mission Partner requirements

Slide-15 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory HPCS Benchmark Spectrum Future and Emerging Applications Identifying HPCS Mission Partner efforts –10-20K processor — Teraflop/s scale applications –20-120K processor — Teraflop/s scale applications –Petascale/s applications –Applications beyond Petascale/s LACSI Workshop — The Path to Extreme Supercomputing –12 October 2004 – What new challenges will arise from Petascale/s+ applications?

Slide-16 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Outline HPCS Benchmark Spectrum What Makes HPC Applications Challenging? –Memory access patterns/locality –Processor characteristics –Parallelism –I/O characteristics –What new challenges will arise from Petascale/s+ applications? Bottleneckology –Amdahl’s Law –Example: Random Stride Memory Access Summary

Slide-17 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Bottleneckology –Where is performance lost when an application is run on an architecture? –When does it make sense to invest in architecture to improve application performance? –System analysis driven by an extended Amdahl’s Law  Amdahl’s Law is not just about parallel and sequential parts of applications! References: –Jack Worlton, "Project Bottleneck: A Proposed Toolkit for Evaluating Newly-Announced High Performance Computers", Worlton and Associates, Los Alamos, NM, Technical Report No.13,January 1988 –Montek Singh, “Lecture Notes — Computer Architecture and Implementation: COMP 206”, Dept. of Computer Science, Univ. of North Carolina at Chapel Hill, Aug 30, fall-04/lectures/lecture-2.ppt

Slide-18 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Lecture Notes — Computer Architecture and Implementation (5) ‡ ‡ Montek Singh (UNC)

Slide-19 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Lecture Notes — Computer Architecture and Implementation (6) ‡ ‡ Montek Singh (UNC)

Slide-20 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Lecture Notes — Computer Architecture and Implementation (7) ‡ Also works for Rate = Bandwidth! ‡ Montek Singh (UNC)

Slide-21 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Lecture Notes — Computer Architecture and Implementation (8) ‡ ‡ Montek Singh (UNC)

Slide-22 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Bottleneck Example (1) Combine stride 1 and random stride memory access –25% random stride access –33% random stride access Memory bandwidth performance is dominated by the random stride memory access SDSC MAPS on an IBM SP-3

Slide-23 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Bottleneck Example (2) Combine stride 1 and random stride memory access –25% random stride access –33% random stride access Memory bandwidth performance is dominated by the random stride memory access SDSC MAPS on a COMPAQ Alphaserver Amdahl’s Law [ 7000 / (7* ) ] = 2800 MB/s

Slide-24 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Bottleneck Example (2) Combine stride 1 and random stride memory access –25% random stride access –33% random stride access Memory bandwidth performance is dominated by the random stride memory access SDSC MAPS on a COMPAQ Alphaserver Amdahl’s Law [ 7000 / (7* ) ] = 2800 MB/s Some HPCS Mission Partner applications –Extensive random stride memory access –Some random stride memory access However, even a small amount of random memory access can cause significant bottlenecks! Some HPCS Mission Partner applications –Extensive random stride memory access –Some random stride memory access However, even a small amount of random memory access can cause significant bottlenecks!

Slide-25 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Outline HPCS Benchmark Spectrum What Makes HPC Applications Challenging? –Memory access patterns/locality –Processor characteristics –Parallelism –I/O characteristics –What new challenges will arise from Petascale/s+ applications? Bottleneckology –Amdahl’s Law –Example: Random Stride Memory Access Summary

Slide-26 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory Summary (1) Memory access patterns/locality –Spatial and Temporal  Indirect addressing  Data dependencies Processor characteristics –Processor throughput (Instructions per cycle)  Low arithmetic density  Floating point versus integer –Special features  GF(2) math  Popcount  Integer division Parallelism –Ubiquitous for Petascale/s –Load balance I/O characteristics –Bandwidth –Latency –File access patterns –File generation rates What makes Applications Challenging! Expand this List as required Work toward consensus with –HPCS Mission Partners –HPCS Vendors Understand Bottlenecks Characterize applications Characterize architectures Expand this List as required Work toward consensus with –HPCS Mission Partners –HPCS Vendors Understand Bottlenecks Characterize applications Characterize architectures

Slide-27 What Makes HPC Applications Challenging MITRE ISIMIT Lincoln Laboratory HPCS Benchmark Spectrum What Makes HPC Applications Challenging? Full applications may be challenging due to –Killer Kernels –Global data layouts –Input/Output Killer Kernels are challenging because of many things that link directly to architecture Identify bottlenecks by mapping applications to architectures Impress upon the HPCS community to identify what makes the application challenging when using an existing Mission Partner application for a systems analysis in the MS4 review